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TPS70751PWP Datasheet(PDF) 10 Page - Texas Instruments |
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TPS70751PWP Datasheet(HTML) 10 Page - Texas Instruments |
10 / 40 page www.ti.com Detailed Description Pin Functions Enable Sequence TPS70745, TPS70748 TPS70751, TPS70758 TPS70702 SLVS291D – MAY 2000 – REVISED DECEMBER 2007 Table 1. TERMINAL FUNCTIONS TERMINAL I/O DESCRIPTION NAME NO. EN 6 I Active low enable GND 8 — Ground MR1 4 I Manual reset input 1, active low, pulled up internally MR2 5 I Manual reset input 2, active low, pulled up internally NC 1, 11, 20 — No connection Open drain output, low when VOUT1 voltage is less than 95% of the nominal regulated PG1 16 O voltage RESET 15 O Open drain output, SVS (power-on reset) signal, active low Power-up sequence control: SEQ = High, VOUT2 powers up first; SEQ 7 I SEQ = Low, VOUT1 powers up first, SEQ terminal pulled up internally. VIN1 2, 3 I Input voltage of regulator 1 VIN2 9, 10 I Input voltage of regulator 2 VOUT1 18, 19 O Output voltage of regulator 1 VOUT2 12, 13 O Output voltage of regulator 2 VSENSE2/FB2 14 I Regulator 2 output voltage sense/regulator 2 feedback for adjustable VSENSE1/FB1 17 I Regulator 1 output voltage sense/regulator 1 feedback for adjustable The TPS707xx low dropout regulator family provides dual regulated output voltages for DSP applications that require high-performance power management solutions. These devices provide fast transient response and high accuracy with small output capacitors, while drawing low quiescent current. Programmable sequencing provides a power solution for DSPs without any external component requirements. This architecture reduces the component cost and board space while increasing total system reliability. The TPS707xx family has an enable feature that puts the device in sleep mode, reducing the input currents to less than 3 µA. Other features are integrated SVS (Power-On Reset, RESET) and Power Good (PG1) that monitor output voltages and provide logic output to the system. These differentiated features provide a complete DSP power solution. The TPS707xx, unlike many other LDOs, feature very low quiescent current that remains virtually constant even with varying loads. Conventional LDO regulators use a pnp pass element, the base current of which is directly proportional to the load current through the regulator (IB = IC/β). The TPS707xx uses a PMOS transistor to pass current; because the gate of the PMOS is voltage=driven, operating current is low and stable over the full load range. The EN terminal is an input that enables or shuts down the device. If EN is at a voltage high signal, the device is in shutdown mode. When EN goes to voltage low, the device is enabled. The SEQ terminal is an input that programs which output voltage (VOUT1 or VOUT2) turns on first. When the device is enabled and the SEQ terminal is pulled high or left open, VOUT2 turns on first and VOUT1 remains off until VOUT2 reaches approximately 83% of its regulated output voltage. At that time, VOUT1 is turned on. If VOUT2 is pulled below 83% (for example, in an overload condition) VOUT1 is turned off. These terminals have a 6-µA pullup current to VIN1. Pulling the SEQ terminal low reverses the power-up order and VOUT1 is turned on first. For detailed timing diagrams, refer to Figure 36 through Figure 40. 10 Submit Documentation Feedback Copyright © 2000–2007, Texas Instruments Incorporated |
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