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TPS73618MDBVREP Datasheet(PDF) 4 Page - Texas Instruments

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Part # TPS73618MDBVREP
Description  CAP-FREE NMOS 400 mA LOW-DROPOUT REGULATORS WITH REVERSE CURRENT PROTECTION
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

TPS73618MDBVREP Datasheet(HTML) 4 Page - Texas Instruments

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ABSOLUTE MAXIMUM RATINGS
POWER DISSIPATION RATINGS
(1)
TPS73601-EP, TPS73615-EP, TPS73618-EP
TPS73625-EP, TPS73630-EP, TPS73632-EP, TPS73633-EP
SGLS326C – APRIL 2006 – REVISED FEBRUARY 2009 .................................................................................................................................................. www.ti.com
over operating free-air temperature range unless otherwise noted
(1)
UNIT
VIN range
–0.3 to 6
V
VEN range
–0.3 to 6
V
VOUT range
–0.3 to 5.5
V
Peak output current
Internally limited
Output short-circuit duration
Indefinite
Continuous total power dissipation
See Dissipation Ratings Table
Junction temperature range, TJ
–55 to 150
°C
Storage temperature range
–65 to 150
°C
Human-Body Model - HBM
2
kV
ESD rating
Charged-Device Model - CDM
500
V
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under the Electrical Characteristics
is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
DERATING FACTOR
TA ≤ 25°C
TA = 70°C
TA = 85°C
BOARD
PACKAGE
RθJC
RθJA
ABOVE TA = 25°C
POWER RATING
POWER RATING
POWER RATING
Low-K(2)
DBV
64°C/W
255°C/W
3.9 mW/°C
392 mW
216 mW
157 mW
High-K(3)
DBV
64°C/W
180°C/W
5.6 mW/°C
556 mW
306 mW
222 mW
Low-K(2)
DCQ
15°C/W
53°C/W
18.9 mW/°C
1887 mW
1038 mW
755 mW
High-K(3)
DCQ
15°C/W
45°C/W
22.2 mW/°C
2222 mW
1222 mW
889 mW
High-K(3)(4)
DRB
1.2°C/W
40°C/W
25.0 mW/°C
2500 mW
1375 mW
1000 mW
(1)
See the Thermal Protection section for more information related to thermal design.
(2)
The JEDEC Low-K (1s) board design used to derive this data was a 3 in × 3 in, two-layer board with 2 oz copper traces on top of the
board.
(3)
The JEDEC High-K (2s2p) board design used to derive this data was a 3 in × 3 in, multilayer board with 1 oz internal power and ground
planes, and 2-oz copper traces on the top and bottom of the board.
(4)
Based on preliminary thermal simulations.
4
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Copyright © 2006–2009, Texas Instruments Incorporated
Product Folder Link(s): TPS73601-EP TPS73615-EP TPS73618-EP TPS73625-EP TPS73630-EP TPS73632-EP
TPS73633-EP


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