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TPS74401RGRR Datasheet(PDF) 4 Page - Texas Instruments |
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TPS74401RGRR Datasheet(HTML) 4 Page - Texas Instruments |
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4 / 40 page  IN IN IN PG BIAS OUT OUT OUT NC FB/SNS TPS744xx 6 7 8 9 10 20 19 18 17 16 GND OUT GND BIAS IN FB/ SNS SS 1 2 3 4 5 6 EN 7 TPS74401 SBVS066Q – DECEMBER 2005 – REVISED APRIL 2015 www.ti.com 5 Pin Configuration and Functions RGW Package KTW Package 5-mm × 5-mm VQFN-20 DDPAK-7 Top View Surface-Mount Pin Functions PIN I/O DESCRIPTION NAME KTW RGW Bias input voltage for error amplifier, reference, and internal control circuits. BIAS 6 10 I A 1-µF or larger input capacitor is recommended for optimal performance. If IN is connected to BIAS, use a 4.7 µF or larger capacitor. Enable pin. Driving this pin high enables the regulator. Driving this pin low puts the EN 7 11 I regulator into shutdown mode. This pin must not be left floating. This pin is the feedback connection to the center tap of an external resistor divider FB 2 16 I network that sets the output voltage. This pin must not be left floating. (Adjustable version only.) GND 4 12 — Ground Unregulated input to the device. IN 5 5–8 I An input capacitor of 1 µF or greater is recommended for optimal performance. 2–4, 13, No connection. This pin can be left floating or connected to GND to allow better thermal NC N/A O 14, 17 contact to the top-side plane. Regulated output voltage. No capacitor is required on this pin for stability, but is OUT 3 1, 18–20 O recommended for optimal performance. Must be soldered to the ground plane for increased thermal performance. PAD/TAB — — — Internally connected to ground. Power-good (PG) is an open-drain, active-high output that indicates the status of VOUT. When VOUT exceeds the PG trip threshold, the PG pin goes into a high-impedance state. When VOUT is below this threshold, the pin is driven to a low-impedance state. Connect PG N/A 9 O a pullup resistor from 10 k Ω to 1 MΩ from this pin to a supply up to 5.5 V. The supply can be higher than the input voltage. Alternatively, the PG pin can be left floating if output monitoring is not necessary. This pin is the sense connection to the load device. SNS 2 16 I This pin must be connected to VOUT and must not be left floating. (Fixed versions only.) Soft-start pin. A capacitor connected on this pin to ground sets the start-up time. SS 1 15 — If this pin is left floating, the regulator output soft-start ramp time is typically 100 µs. 4 Submit Documentation Feedback Copyright © 2005–2015, Texas Instruments Incorporated Product Folder Links: TPS74401 |
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