TPS74401RGWR datasheet(6/40 Pages) TI1

Part #	TPS74401RGWR

Description	3.0-A, Ultra-LDO with Programmable Soft-Start

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Manufacturer	TI1 [Texas Instruments]

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6 / 40 page

TPS74401

SBVS066Q – DECEMBER 2005 – REVISED APRIL 2015

www.ti.com

6.4 Thermal Information

TPS74401(3)

THERMAL METRIC(1)(2)

RGW (VQFN)

KTW (DDPAK)

UNIT

20 PINS

7 PINS

RθJA

Junction-to-ambient thermal resistance

35.4

26.6

RθJC(top)

Junction-to-case (top) thermal resistance

32.4

41.7

RθJB

Junction-to-board thermal resistance

14.7

12.5

°C/W

ψJT

Junction-to-top characterization parameter

0.4

4.0

ψJB

Junction-to-board characterization parameter

14.8

7.3

RθJC(bot)

Junction-to-case (bottom) thermal resistance

3.9

0.3

(1)

For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2)

For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator.

(3)

Thermal data for the RGW and KTW packages are derived by thermal simulations based on JEDEC-standard methodology as specified

in the JESD51 series. The following assumptions are used in the simulations:

(a) i. RGW: The exposed pad is connected to the PCB ground layer through a 4x4 thermal via array.

- ii. KTW: The exposed pad is connected to the PCB ground layer through a 6x6 thermal via array.

(b) Each of top and bottom copper layers has a dedicated pattern for 20% copper coverage.

(c) These data were generated with only a single device at the center of a JEDEC high-K (2s2p) board with 3in × 3in copper area. To

understand the effects of the copper area on thermal performance, refer to the Thermal Considerations section.

6.5 Electrical Characteristics

At VEN = 1.1 V, VIN = VOUT + 0.3 V, CIN = CBIAS = 0.1 μF, COUT = 10 μF, IOUT = 50 mA, VBIAS = 5.0 V, and TJ = –40°C to 125°C,

unless otherwise noted. Typical values are at TJ = 25°C.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VIN

Input voltage range

VOUT + VDO

5.5

V

VBIAS

Bias pin voltage range

2.375

5.25

V

Internal reference

VREF

TJ = 25°C

0.796

0.8

0.804

V

(adjustable version)

Output voltage range

VIN = 5 V, IOUT = 1.5 A, VBIAS = 5 V

VREF

3.6

V

2.97 V

≤ VBIAS ≤ 5.25 V, VOUT + 1.62 V ≤ VBIAS,

–1%

±0.2%

1%

VOUT

50 mA

≤ IOUT ≤ 3.0 A

(1)

Accuracy

VOUT + VDO BIAS ≤ VBIAS ≤ 5.25 V,

–1%

±0.2%

1%

100 mA

≤ IOUT ≤ I VDO BIAS , VQFN

(2)

VOUT(nom) + 0.3 ≤ VIN ≤ 5.5 V, VQFN

0.0005

0.05

%/V

ΔVOUT(ΔVIN)

Line regulation

VOUT(nom) + 0.3 ≤ VIN ≤ 5.5 V, DDPAK

0.0005

0.06

%/V

0 mA

≤ IOUT ≤ 50 mA

0.013

%/mA

ΔVOUT(ΔIOUT) Load regulation

50 mA

≤ IOUT ≤ 3.0 A

0.03

%/A

IOUT = 3.0 A, VBIAS – VOUT(nom) ≥ 1.62 V, VQFN

115

195

mV

VIN dropout voltage

(3)

IOUT = 3.0 A, VBIAS – VOUT(nom) ≥ 1.62 V, DDPAK

120

240

mV

IOUT = 3.0 A, VIN = VBIAS

1.62

V

VDO

IOUT = 3.0 A

1.62

V

VBIAS dropout voltage

(3)

IOUT = 1.0 A

1.35

V

IOUT = 500 mA

1.27

V

IOUT = 100 mA

1.16

V

VOUT = 80% × VOUT(nom), VQFN

3.8

6.0

A

ICL

Current limit

VOUT = 80% × VOUT(nom), DDPAK

3.5

6.0

A

IBIAS

Bias pin current

IOUT = 0 mA to 3.0 A

2

4

mA

ISHDN

Shutdown supply current (VIN)

VEN ≤ 0.4 V

1

100

μA

IFB, ISNS

Feedback, sense pin current(4)

IOUT = 50 mA to 3.0 A

–250

95

250

nA

(1)

Adjustable devices tested at 0.8 V; external resistor tolerance is not taken into account.

(2)

VOUT is set to 1.5 V to avoid minimum VBIAS restrictions.

(3)

Dropout is defined as the voltage from the input to VOUT when VOUT is 2% below nominal.

(4)

IFB, ISNS current flow is out of the device.

6

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