TPS75201Q1, '75215Q1, '75218Q1, '75225Q1, '75233Q1 WITH RESET

TPS75401Q1, '75415Q1, '75418Q1, '75425Q1, '75433Q1 WITH POWER GOOD

FAST TRANSIENT RESPONSE 2A LOW DROPOUT VOLTAGE REGULATORS

SGLS166C − APRIL 2003 – REVISED APRIL 2008

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POST OFFICE BOX 655303

MIL-STD-883, Method 3015; Exceeds 200 V

Using Machine Model (C = 200 pF, R = 0)

Output and Adjustable Versions

Delay (TPS752xx)

Output (TPS754xx)

(TPS75233)

for Fixed-Output Versions

description

The TPS752xx and TPS754xx are low-dropout regulators with integrated power-on reset and power good (PG)

functions, respectively. These devices are capable of supplying 2 A of output current with a dropout of 210 mV

(TPS75233, TPS75433). Quiescent current is 75

µA at full load and drops down to 1 µA when the device is disabled.

TPS752xx and TPS754xx are designed to have fast transient response for larger load current changes.

Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 210 mV at an

output current of 2 A for the TPS75x33) and is directly proportional to the output current. Additionally, since the

PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output loading

(typically 75

µA over the full range of output current, 1 mA to 2 A). These two key specifications yield a significant

improvement in operating life for battery-powered systems.

The device is enabled when the EN pin is connected to a low-level input voltage. This LDO family also features a

sleep mode; applying a TTL high signal to EN (enable) shuts down the regulator, reducing the quiescent current

to 1

The RESET (SVS, POR, or power on reset) output of the TPS752xx initiates a reset in microcomputer and

microprocessor systems in the event of an undervoltage condition. An internal comparator in the TPS752xx

monitors the output voltage of the regulator to detect an undervoltage condition on the regulated output voltage.

When the output reaches 95% of its regulated voltage, RESET goes to a high-impedance state after a 100-ms delay.

RESET goes to a logic-low state when the regulated output voltage is pulled below 95% (i.e., over load condition)

of its regulated voltage.

Copyright

 2008, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

PowerPAD is a trademark of Texas Instruments.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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PWP PACKAGE

(TOP VIEW)

GND/HEATSINK

NC

IN

IN

EN

FB/SENSE

OUTPUT

OUTPUT

GND/HEATSINK

GND/HEATSINK

NC

NC

GND

NC

NC

NC

NC

NC

GND/HEATSINK

NC − No internal connection

‡ PG is on the TPS754xx and RESET is on the TPS752xx