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TPS726 Datasheet(PDF) 4 Page - Texas Instruments |
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TPS726 Datasheet(HTML) 4 Page - Texas Instruments |
4 / 23 page TPS726126/15/16 OUT IN GND EN Vref Current Limit / Thermal Protection 0.93 × Vref Deglitch and Delay RESET 1.220 NOTES:A. VRES is the minimum input voltage for a valid RESET. IN VRES (see Note A) VRES t t t OUT Threshold Voltage RESET Output 200 ms Delay 200 ms Delay Output Undefined Output Undefined VIT+ VIT− VIT+ VIT− TPS726126 TPS72615, TPS72616 TPS72618, TPS72625 SLVS403H – MAY 2002 – REVISED JUNE 2010 www.ti.com FUNCTIONAL BLOCK DIAGRAM Terminal Functions TERMINAL DESCRIPTION NAME NO. GND 3 Ground ENABLE 1 Enable input IN 2 Input supply voltage RESET 5 This terminal is the RESET output. When used with a pull-up resistor, this open-drain output provides the active low RESET signal when the regulator output voltage drops more than 5% below its nominal output voltage. The RESET delay time is typically 200 ms. OUT 4 Regulated output voltage RESET TIMING DIAGRAM 4 Submit Documentation Feedback Copyright © 2002–2010, Texas Instruments Incorporated Product Folder Link(s): TPS726126 TPS72615 TPS72616 TPS72618 TPS72625 |
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