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ICS8761 Datasheet(PDF) 11 Page - Integrated Circuit Systems |
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ICS8761 Datasheet(HTML) 11 Page - Integrated Circuit Systems |
11 / 15 page 8761CY www.icst.com/products/hiperclocks.html REV. C SEPTEMBER 7, 2004 11 Integrated Circuit Systems, Inc. ICS8761 LOW VOLTAGE, LOW SKEW, PCI / PCI-X CLOCK GENERATOR SCHEMATIC EXAMPLE Figure 3 shows a schematic example of the ICS8761. In this example, the input is driven by an ICS HiPerClockS LVHSTL driver. The decoupling capacitors should be physically located near the power pin. For ICS8761, the unused clock outputs can be left floating. The optional C1 and C2 are spare footprints for frequency fine tuning. FIGURE 3. ICS8761 CLOCK GENERATOR SCHEMATIC EXAMPLE Receiv er RU1 1K (U1,23) C16 10u VDDO C17 0.1u VDD SP = Spare, Not Install (U1,44) VDD=3.3V Zo = 50 Zo = 50 C9 0.1u U1 ICS8761 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 39 38 37 36 35 34 33 48 47 46 45 44 43 42 41 40 REF_CLK GND XTAL1 XTAL2 VDD XTAL_SEL PLL_SEL VDDA VDD D_SELC0 D_SELC1 OEC OEA D_SELA0 D_SELA1 GND D_SELD0 D_SELD1 OED OEB D_SELB0 D_SELB1 GND GND FB_OUT VDDOFB FB_IN VDD FBDIV_SEL0 FBDIV_SEL1 MR VDD VDD (U1,46) Set Logic Input to '1' VDDO VDD RD1 SP To Logic Input pins R6 1K C5 0.1u C12 0.1u Receiv er VDDO=3.3V Set Logic Input to '0' C3 0.1u VDD R3 36 R5 1K To Logic Input pins C15 0.1u R4 36 Receiv er Zo = 50 C13 0.1u Logic Input Pin Examples C2 SP (U1,5) VDDO X1 25MHz,18pF (U1,40) (U1,19) C1 SP RD2 1K VDDO C8 0.1u C11 0.1u R1 36 C6 0.1u VDD (U1,58) C10 0.1u Zo = 50 R2 36 (U1,62) VDD C14 0.1u Receiv er (U1,50) (U1,9) (U1,31) (U1,54) VDD C7 0.1u RU2 SP R7 10 (U1,27) C4 0.1u |
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