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ICS8761CYLF Datasheet(PDF) 1 Page - Integrated Circuit Systems |
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ICS8761CYLF Datasheet(HTML) 1 Page - Integrated Circuit Systems |
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1 / 15 page  8761CY www.icst.com/products/hiperclocks.html REV. C SEPTEMBER 7, 2004 1 Integrated Circuit Systems, Inc. ICS8761 LOW VOLTAGE, LOW SKEW, PCI / PCI-X CLOCK GENERATOR OEA MR D_SELA0 D_SELA1 REF_CLK XTAL_SEL FB_IN PLL_SEL OEB D_SELB1 D_SELB0 OEC D_SELC1 D_SELC0 OED D_SELD1 D_SELD0 FBDIV_SEL1 FBDIV_SEL0 GENERAL DESCRIPTION The ICS8761 is a low voltage, low skew PCI / PCI-X Clock Generator and a member of the HiPerClockS™family of High Performance Clock Solutions from ICS. The ICS8761 has a selectable REF_CLK or crystal input. The REF_CLK input accepts LVCMOS or LVTTL input levels. The ICS8761 has a fully integrated PLL along with frequency configurable clock and feedback outputs for multiplying and regenerating clocks with “zero delay”. Using a 20MHz or 25MHz crystal or a 33.333MHz or 66.666MHz reference frequency, the ICS8761 will generate output frequencies of 33.333MHz, 66.666MHz, 100MHz and 133.333MHz simultaneously. The low impedance LVCMOS/LVTTL outputs of the ICS8761 are designed to drive 50 Ω series or parallel terminated transmission lines. FEATURES • Fully integrated PLL • 17 LVCMOS/LVTTL outputs, 15Ω typical output impedance • Selectable crystal oscillator interface or LVCMOS/LVTTL REF_CLK • Maximum output frequency: 166.67MHz • Maximum crystal input frequency: 38MHz • Maximum REF_CLK input frequency: 83.33MHz • Individual banks with selectable output dividers for generating 33.333MHz, 66.66MHz, 100MHz and 133.333MHz simultaneously • Separate feedback control for generating PCI / PCI-X frequencies from a 20MHz or 25MHz crystal or 33.333MHz or 66.666MHz reference frequency • Cycle-to-cycle jitter: 70ps (maximum) • Period jitter, RMS: 17ps (maximum) • Output skew: 230ps (maximum) • Bank skew: 40ps (maximum) • Static phase offset: 0 ± 150ps (maximum) • Full 3.3V or 3.3V core, 2.5V multiple output supply modes • 0°C to 85°C ambient operating temperature • Lead-Free package available HiPerClockS™ ICS BLOCK DIAGRAM PIN ASSIGNMENT XTAL1 XTAL2 QA0 QA1 QA2 QA3 QB0 QB1 QB2 QB3 FB_OUT ÷3 ÷4 ÷6 ÷12 0 0 0 1 1 0 1 1 0 1 0 0 0 1 1 0 1 1 QC0 QC1 QC2 QC3 QD0 QD1 QD2 QD3 PLL OSC 0 1 ÷6 ÷12 ÷16 ÷20 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 64-Lead LQFP 10mm x 10mm x 1.4mm package body Y package Top View ICS8761 REF_CLK GND XTAL1 XTAL2 VDD XTAL_SEL PLL_SEL VDDA VDD D_SELC0 D_SELC1 OEC OEA D_SELA0 D_SELA1 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 GND FB_OUT VDDOFB FB_IN VDD FBDIV_SEL0 FBDIV_SEL1 MR VDD D_SELD0 D_SELD1 OED OEB D_SELB0 D_SELB1 GND 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 |
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