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IDT7028L20PFI Datasheet(PDF) 11 Page - Integrated Device Technology |
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IDT7028L20PFI Datasheet(HTML) 11 Page - Integrated Device Technology |
11 / 17 page 6.42 IDT7028L High-Speed 64K x 16 Dual-Port Static RAM Industrial and Commercial Temperature Ranges 11 4836 drw 11 tDW tAPS ADDR"A" tWC DATAOUT "B" MATCH tWP R/ W"A" DATAIN "A" ADDR"B" tDH VALID (1) MATCH BUSY"B" tBDA VALID tBDD tDDD (3) tWDD tBAA Timing Waveform of Write with Port-to-Port Read and BUSY(M/S = VIH)(2,4,5) Timing Waveform of Write with BUSY (M/S = VIL) NOTES: 1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/ S = VIL (SLAVE). 2. CEL = CER = VIL, refer to Chip Enable Truth Table. 3. OE = VIL for the reading port. 4. If M/ S = VIL (SLAVE), BUSY is an input. Then for this example BUSY"A" = VIH and BUSY"B" input is shown above. 5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A". NOTES: 1. tWH must be met for both BUSY input (SLAVE) and output (MASTER). 2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH. 3. tWB is only for the 'Slave' version. 4836 drw 12 R/ W"A" BUSY"B" tWP tWB(3) R/ W"B" tWH (1) (2) . |
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