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TPS79147DBVTG4 Datasheet(PDF) 2 Page - Texas Instruments |
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TPS79147DBVTG4 Datasheet(HTML) 2 Page - Texas Instruments |
2 / 23 page 3 2 4 5 DBV PACKAGE (TOP VIEW) 1 IN GND EN OUT BYPASS 3 2 4 6 DBV PACKAGE (TOP VIEW) 1 IN EN OUT BYPASS 5 FB Adjustable Option Fixed Option 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 100 1 k 10 k 100 k IO = 1 mA VO = 4.3 V Co = 1 µF C(byp) = 0.1 µF IO = 100 mA f − Frequency − Hz TPS79133 OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY 60 50 30 20 10 100 1 k 10 k 70 90 100 100 k 1 M 10 M 40 80 f − Frequency − Hz TPS79133 RIPPLE REJECTION vs FREQUENCY VI = 4.3 V Co = 10 µF C(byp) = 0.01 µF IO = 10 mA IO = 100 mA GND ABSOLUTE MAXIMUM RATINGS (1) TPS79101-EP, TPS79118-EP TPS79133-EP, TPS79147-EP SGLS161A – APRIL 2003 – REVISED JUNE 2008 ............................................................................................................................................................ www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. over operating free-air temperature range (unless otherwise noted) TPS79101, TPS79118, TPS79133, TPS79147 Input voltage range(2) –0.3 V to 6 V Voltage range at EN –0.3 V to VI + 0.3 V Voltage on OUT –0.3 V to 6 V Peak output current Internally limited ESD rating, HBM 2 kV ESD rating, CDM 500 V Continuous total power dissipation See Dissipation Rating Table All others –40°C to 150°C Operating virtual-junction temperature range, TJ TPS79133MDBVTEP –55°C to 125°C All others –40°C to 120°C Operating ambient temperature range, TA TPS79133MBVTEP –55°C to 125°C Storage temperature range, Tstg –65°C to 150°C Low K 63.75°C/W RθJC (3) High K 63.75°C/W Low K 256°C/W RθJA (4) High K 178.3°C/W (1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values are with respect to network ground terminal. (3) The JEDEC low-K (1s) board design used to derive this data was a 3-inch × 3-inch, two-layer board with 2-ounce copper traces on top of the board. (4) The JEDEC high-K (2s2p) board design used to derive this data was a 3-inch × 3-inch, multilayer board with 1-ounce internal power and ground planes and 2-ounce copper traces on top and bottom of the board. 2 Submit Documentation Feedback Copyright © 2003–2008, Texas Instruments Incorporated Product Folder Link(s): TPS79101-EP TPS79118-EP TPS79133-EP TPS79147-EP |
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