LC75806PT

No.A1425-9/35

(2) When CL is stopped at the high level

Note: B0 to B3, A0 to A3 ········· CCB address

DD ································· Direction data

• CCB address ···············“42H”

• D1 to D304 ·················Display data

• OC ······························RC oscillator operating mode/external clock operationg mode switching control data

• PC90, PC91·················General-purpose output port/clock output port/segment output port switching control data

• S0, S1··························Sleep control data

• K0, K1 ························Key scan output/segment output switching control data

• P0 to P3·······················Segment output port/general-purpose output port switching control data

• SC·······························Segment on/off control data

• KSC ····························Key scan operation enabled/disabled state setting control data

• FC0 to FC2 ·················Common and segment output waveform frame frequency control data

• CT0 to CT2 ·················Display contrast setting control data

1

0

B1

B0

D2

D1

D74

S1

0

0

0

0

1

0

0

B3

B2

A1

A0

A3

A2

D75

0

00

KSC

SC

P3

P2

0

0

0

P1

K0 K1 P0

D76

D71 D72 D73

S0

PC91

PC90

OC

DI

CL

CE

DO

CT2

CT1

CT0

FC2

1

0

0

FC1

FC0

0

0

0

0

0

0

0

0

0

0

0

D152

D151

D150

D149

D148

D147

B1

B0

D78

D77

1

0

0

0

0

1

0

0

B3

B2

A1

A0

A3

A2

B1

B0

B3

B2

A1

A0

A3

A2

0

0

0

0

0

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

D228

D227

D226

D225

D224

D223

1

0

0

0

0

1

0

0

D154

D153

B1

B0

1

0

0

0

0

1

0

0

B3

B2

A1

A0

A3

A2

0

0

0

0

1

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

D304

D303

D302

D301

D300

D299

D230

D229

DD

(3 bits)

Control data (17 bits)

Display data (76 bits)

Fixed data (17 bits)

DD

(3 bits)

Control data (17 bits)

Display data (76 bits)

DD

(3 bits)

Display data (76 bits)

Fixed data (17 bits)

DD

(3 bits)

Display data (76 bits)