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TSB12LV22 Datasheet(PDF) 9 Page - Texas Instruments |
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TSB12LV22 Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 45 page  TSB12LV22 OHCI-Lynx PCI-BASED IEEE 1394 HOST CONTROLLER SLLS290A − JULY 1998 − REVISED NOVEMBER 1998 9 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI status register PCI Bus Specification, as seen in the bit descriptions. PCI register 06h BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 Table 5. Bit Descriptions − PCI Status Register BIT FIELD NAME ACCESS DESCRIPTION 15 PAR_ERR rcu Detected parity error. This bit is set when a parity error is detected, either address or data parity errors. 14 SYS_ERR rcu Signaled system error. This bit is set when SERR is enabled and the OHCI-Lynx signaled a system error to the host. 13 MABORT rcu Received master abort. This bit is set when a cycle initiated by the OHCI-Lynx on the PCI bus has been terminated by a master abort. 12 TABORT_REC rcu Received target abort. This bit is set when a cycle initiated by the OHCI-Lynx on the PCI bus was terminated by a target abort. 11 TABORT_SIG rcu Signaled target abort. This bit is set by the OHCI-Lynx when it terminates a transaction on the PCI bus with a target abort. 10:9 PCI_SPEED r DEVSEL timing. These read only bits encode the timing of DEVSEL and are hardwired 01b indicating that the OHCI-Lynx asserts this signal at a medium speed on non-configuration cycle accesses. 8 DATAPAR rcu Data parity error detected. This bit is set when the following conditions have been met: a. PERR# was asserted by any PCI device including the OHCI-Lynx b. The OHCI-Lynx was the bus master during the data parity error c. The parity error response bit is set in the command register 7 FBB_CAP r Fast back-to-back capable. The OHCI-Lynx cannot accept fast back to back transactions; thus, this bit is hardwired to zero. 6 UDF r UDF supported. The OHCI-Lynx does not support the user definable features; thus, this bit is hardwired to zero. 5 66MHZ r 66 MHz capable. The OHCI-Lynx operates at a maximum PCLK frequency of 33 MHz; therefore, this bit is hardwired to zero. 4 CAPLIST r Capabilities list. This bit is read only and returns one when read. It indicates that capabilities additional to standard PCI are implemented. The linked list of PCI Power Management capabilities is implemented in this function. class code and revision ID register This read only register categorizes the OHCI-Lynx as a serial bus controller (0Ch), controlling an IEEE1394 bus (00h), with an OHCI programming model (10h). Furthermore, the TI chip revision is indicated in the lower byte. PCI register 08h BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset State 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 |
Similar Part No. - TSB12LV22_12 |
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Similar Description - TSB12LV22_12 |
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