R3920-CFAB-E1T datasheet(6/13 Pages) ONSEMI

Part #	R3920-CFAB-E1T

Description	Preconfigured DSP System for Hearing Aids

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6

Table 3. I2C TIMING

Parameter

Symbol

Standard Mode

Fast Mode

Units

Min

Max

Min

Max

Clock Frequency

fPC_CLK

0

100

0

400

kHz

Hold time (repeated) START condition. After this

period, the first clock pulse is generated.

tHD;STA

4.0

−

0.6

−

msec

LOW Period of the PC_CLK Clock

tLOW

4.7

−

msec

HIGH Period of the PC_CLK Clock

tHIGH

4.0

−

msec

Set−up time for a repeated START condition

tSU;STA

4.7

−

msec

Data Hold Time:

for CBUS Compatible Masters

for I2C−bus Devices

tHD;DAT

5.0

0 (Note 1)

−

3.45 (Note 2)

−

0 (Note 1)

−

0.9 (Note 2)

msec

Data set−up time

tSU;DAT

250

−

100

−

nsec

Rise time of both PC_SDA and PC_CLK signals

tr

−

1000

20 + 0.1 Cb

(Note 4)

300

nsec

Fall time of both PC_SDA and PC_CLK signals

tf

−

300

20 + 0.1 Cb

(Note 4)

300

nsec

Set−up time for STOP condition

tSU;STO

4.0

−

0.6

−

nsec

Bus free time between a STOP and

START condition

tBUF

4.7

−

1.3

−

msec

Output fall time from VIHmin to VILmax with a bus

capacitance from 10 pF to 400 pF

tof

−

250

20 + 0.1 Cb

250

nsec

Pulse width of spikes which must be suppressed

by the input filter

tSP

n/a

0

50

nsec

Capacitive load for each bus line

Cb

−

400

−

400

pF

1. A device must internally provide a hold time of at least 300 ns for the PC_SDA signal to bridge the undefined region of the falling edge of PC_CLK.

2. The maximum tHD;DAT has only to be met if the device does not stretch the LOW period (tLOW) of the PC_CLK signal.

3. A Fast−mode I2C−bus device can be used in a Standard−mode I2C−bus system, but the requirement tSU;DAT P250ns must then be met.

This will automatically be the case if the device does not stretch the LOW period of the PC_CLK signal. If such a device does stretch the

LOW period of the PC_CLK signal, it must output the next data bit to the PC_SDA line tr max + tSU;DAT = 1000 + 250 = 1250 ns (according

to the Standard−mode I2C−bus specification) before the PC_CLK line is released.

4. Cb = total capacitance of one bus line in pF.

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