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DESCRIPTION

TSB83AA22A

SLLA255 – APRIL 2006

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PCI Burst Transfers and Deep FIFOs to

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Programmable Asynchronous Transmit

Tolerate Large Host Latency:

Threshold

– Transmit FIFO—5K Asynchronous

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Isochronous Receive Dual-Buffer Mode

– Transmit FIFO—2K Isochronous

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Out-of-Order Pipelining for Asynchronous

Transmit Requests

– Receive FIFO—2K Asynchronous

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Initial-Bandwidth-Available and

– Receive FIFO—2K Isochronous

Initial-Channels-Available Registers

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D0, D1, D2, and D3 Power States and PME

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Digital Video and Audio Performance

Events per the PCI Bus Power Management

Enhancements

Interface Specification

The TSB83AA22A is an IEEE Std 1394b-2002 link-layer design and Phy design combined in a single package to

meet the demanding requirements of today’s 1394 bus applications. The TSB83AA22A device is capable of

exceptional 800-Mbps performance; thus, providing the throughput and bandwidth to move data efficiently and

quickly between the PCI and 1394 buses. The TSB83AA22A device also provides outstanding ultralow-power

operation and intelligent power management capabilities. The device provides the IEEE 1394 LLC function and

Phy function and is compatible with 100 Mbps, 200 Mbps, 400 Mbps, and 800 Mbps serial-bus data rates.

The TSB83AA22A operates as the interface between 33-MHz/32-bit PCI local bus and an IEEE Std 1394a-2000

or IEEE Std 1394b-2002 serial bus interface. It is capable of supporting serial data rates at 98.304, 196.608,

393.216, 491.52, or 786.432 Mbps (referred to as S100, S200, S400, S400B, or S800 speeds, respectively).

When acting as a PCI bus master, the TSB83AA22A device is capable of multiple cacheline bursts of data,

which can transfer at 132M bytes/s for 32-bit transfers after connecting to the memory controller.

Due to the high throughput potential of the TSB83AA22A device, it possible to encounter large PCI and legacy

1394 bus latencies, which can cause the 1394 data to be overrun. To overcome this potential problem, the

TSB83AA22A implements deep transmit and receive FIFOs (see Section 1.1, Features, for FIFO size

information) to buffer the 1394 data, thus preventing possible problems due to bus latency. This also ensures

that the device can transmit and receive sustained maximum-size isochronous or asynchronous data payloads

at S800.

The TSB83AA22A LLC section implements other performance enhancements to improve overall performance of

the device, such as: a highly tuned physical data path for enhanced SBP-2 performance, physical post writing

buffers, multiple isochronous contexts, and advanced internal arbitration.

The TSB83AA22A LLC section also implements hardware enhancements to better support digital video (DV)

and MPEG data stream reception and transmission. These enhancements are enabled through the isochronous

receive digital video enhancements register at TI extension offset A80h (see Section 6.3.4, Isochronous Receive

Digital Video Enhancements Register). These enhancements include automatic time stamp insertion for

transmitted DV and MPEG-formatted streams and common isochronous packet (CIP) header stripping for

received DV streams.

The CIP format is defined by the IEC 61883-1:1998 specification. The enhancements to the isochronous data

contexts are implemented as hardware support for the synchronization timestamp for both DV and audio/video

CIP formats. The TSB83AA22A device supports modification of the synchronization timestamp field to ensure

that the value inserted via software is not stale — that is, less than the current cycle timer when the packet is

transmitted.

The TSB83AA22A performance and enhanced throughput make it an excellent choice for today’s 1394 PC

market; however, the portable, mobile, and even today’s desktop PCs power management schemes continue to

require devices to use less and less power, and Texas Instrument’s 1394 product line has continued to raise the

bar by providing the lowest-power 1394 devices in the industry. The TSB83AA22A device represents the next

evolution of Texas Instruments commitment to meet the challenge of power-sensitive applications. The

TSB83AA22A device has ultralow operational power requirements and intelligent power management

capabilities that allow it to conserve power autonomously based on the device usage. The TSB83AA22A LLC

requirements and the PCI Power Management Specification. PME wake event support is subject to operating

system support and implementation.

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