PC87382 datasheet(10/72 Pages) NSC

Part #	PC87382

Description	LPC-to-LPC Switch for Docking Stations, with Fast Infrared Port, Serial Port and GPIOs

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Manufacturer	NSC [National Semiconductor (TI)]

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1.0 Signal/Pin Connection and Description (Continued)

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10

Revision1.2

1.3

DETAILED SIGNAL/PIN DESCRIPTIONS

This section describes all signals of the PC87382.

1.3.1

LPC Bus Interface

1.3.2

Docking LPC Bus

1.3.3

Clocks

Signal

Pin(s)

I/O

Buffer Type

Description

LAD3-0

40, 38,

36, 32

I/O

INPCI/OPCI

LPC Address-Data. Multiplexed command, address bidirectional data

and cycle status.

LCLK

25

I

INPCI

LPC Clock. Same as PCI clock (up to 33 MHz).

LDRQ

16

O

OPCI

LPC DMA Request. Encoded DMA request for LPC interface.

LFRAME

30

I

INPCI

LPC Frame. Low pulse indicates the beginning of a new LPC cycle or

termination of a broken cycle.

LRESET

27

I

INPCI

LPC Reset. Same as PCI system reset.

SERIRQ

28

I/O

INPCI/OPCI

Serial IRQ. The interrupt requests are serialized over a single pin, where

each IRQ level is delivered during a designated time slot.

CLKRUN

19

I/OD

INPCI/OD6

Clock Run. Same as PCI CLKRUN.

Signal

Pin(s)

I/O

Buffer Type

Description

DLAD3-0

41, 39,

37, 33

I/O

QS

Dock LPC Address-Data. Multiplexed command, address bidirectional

data and cycle status.

DLCLK

26

I/O

QS

Dock LPC Clock. Same as PCI clock (up to 33 MHz).

DLFRAME

31

I/O

QS

Dock LPC Frame. Low pulse indicates the beginning of a new LPC cycle

or termination of a broken cycle.

DSERIRQ

29

I/O

QS

Dock Serial IRQ. The interrupt requests are serialized over a single pin,

where each IRQ level is delivered during a designated time slot.

DCLKRUN

20

I/O

QS

Dock Clock Run. Same as PCI CLKRUN.

DLRESET

18

O

O4/4

Dock LPC Reset. Main LPC Reset combined with Dock LPC enable.

DLDRQ

4

I

INT

Dock LPC DMA Request. Encoded DMA request for LPC interface.

Signal

Pin(s)

I/O

Buffer Type

Description

CLKIN

43

I

INT

Clock In. 14.318 MHz or 48 MHz clock input.

DCLKOUT

42

O

O14/14

Dock Clock Output. Buffered clock for the Docking device. Enabled

together with DLCLK; otherwise in TRI-STATE.

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PC87382 Datasheet(PDF) 10 Page - National Semiconductor (TI)

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