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S5D0127X01-Q0R0 Datasheet(PDF) 8 Page - Samsung semiconductor |
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S5D0127X01-Q0R0 Datasheet(HTML) 8 Page - Samsung semiconductor |
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8 / 96 page  ELECTRONICS S5D0127X01 Data Sheet MULTIMEDIA VIDEO PAGE 8 OF 96 Modified on May/04/2000 1. FUNCTIONAL DESCRIPTION 1.1. VIDEO INPUT The S5D0127X01 supports complete video decoding of many analog video standards. In addition, the chip can support direct 8-bit YCbCr input for high quality video scaling and other processing. 1.1.1. Analog Video Input Figure 1 shows the detailed block diagram of the analog front end. Up to six composite video sources, three S-video sources, one 3-wire YCbCr component video source, or any combination can be selected. The allowed inputs are selected using the INSEL[3:0] bits in the CMDB register. Table 1 lists all possible input selections. The front end has two paths each containing an analog gain control, a clamping control, and an 8-bit ADC. Composite video input uses only the luma path. S-video and analog component YCbCr inputs utilize both the luma and chroma paths. The ADC digital data is used to calculate the correct gain and clamp values. The data is feedback to the analog clamping and gain control. This architecture eliminates any offset and gain mismatch in the analog front end. Figure 1. Analog Front End The analog inputs must be AC coupled through an external 0.1 µF capacitor clamp. Due to the high sampling rate of the ADC’s inside the S5D0127X01, most video sources will not require a low-pass filter for alias reduction. For those video sources with harmonics above 13 MHz, a simple single order pole at 6 MHz will provide sufficient high frequency signal reduction. This can be implemented with a 400 pF capacitor in parallel with the 75 Ω load. Figure 2. Typical Analog Video Input 8 Bit ADC AGC LPF AY0 AY1 AY2 AC0 AC1 AC2 AGC 8 Bit ADC LPF OFFSET GAIN OFFSET VRT VRB COMP1 To Chroma Processing To Luma Processing To Timing Generation 8-bit Digital Input 75 Ω 0.1 µF Analog Video S5D0127X01 |
Similar Part No. - S5D0127X01-Q0R0 |
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