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S5D2650 Datasheet(PDF) 5 Page - Samsung semiconductor |
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S5D2650 Datasheet(HTML) 5 Page - Samsung semiconductor |
5 / 95 page ELECTRONICS S5D2650 Data Sheet MULTIMEDIA VIDEO PAGE 5 OF 95 7/18/03 PID 17 O PAL ID flag. Pahse Alternate Line flag OEN 15 I Output data, timing and clock 3-state output control. (Default : tied to VDD) CK 18 I/O System clock. (Default : 27MHz output. When the EXV port is used as an input, this can be programmed as an input system clock.) CK2 21 O Pixel rate output clock (Default : 13.5 MHz) CCDAT 73 O Sliced VBI data output. Data can be from Closed Caption, Teletext, Intercast, or WSS type encoded data. CCEN 74 O When high, this pin indicates that valid VBI data is being clocked out at the CCDAT pin or at the digital video output. MULTI-PURPOSE I/O PORTS PORTA 58 I/O Multi-purpose I/O portA. PORTB(SCH) 24 I/O Multi-purpose I/O portB. HOST INTERFACE SCLK 75 I Serial clock for IIC host interface. (5V tolerant schmitt trigger pin) SDAT 72 I/O Serial data for IIC host interface.(5V tolerant schmitt triggered open drain Pins) AEX0 - AEX1 69 - 70 I Device ID selection for IIC host interface. POWER AND GROUND VDD3 9,20,59 3.3V Digital power supply for input, output buffers. VDD1 11,12,42,43,66, 67 1.8V Digital power supply for core logic. VDDA 85,89,93 3.3V Analog power supply for ADC, AGC and reference circuits. VDDP 98 3.3V Analog power supply for clock generation circuit(PLL). VSS 1,2,6,13,14,19, 40,41,49-52,60, 64,65,77-80, 81-83,87,91,95, 96 GND Common ground. VSSP 100 GND Common ground for PLL. PIN DESCRIPTION (Continued) Pin Name Pin # Type Description |
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