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Integrated Silicon Solution, Inc. - www.issi.com

Rev. B

2/5/2015

IS42VS83200J / IS42VS16160J / IS42VS32800J

1.8V (VS) SDRAM Functionality

ISSI’s 256Mb 42VS Series SDRAM IS42VS83200J, IS42VS16160J, and IS42VS32800J, are pin compatible and

have similar functionality with ISSI’s standard 3.3V SDRAMs, but offer lower operating voltages and lower current. For

detailed descriptions of pin functions, command truth tables, functional truth tables, device operation as well as timing

diagrams please refer to datasheets related to IS42S83200J, IS42S16160J, or IS42S32800J, listed at www.issi.com

REGISTER DEFINITION

Mode Register (MR)

There is a mode register in the SDRAM. The Mode Register is used to define the specific mode of operation of the

SDRAM. This definition includes the selection of burst length, a burst type, CAS Latency, operating mode, and a write

burst mode. The mode register is programmed via the LOAD MODE REGISTER command and will retain the stored

information until it is programmed again or the device loses power.

The MR is used to define the specific mode of operation of the SDRAM. This definition includes the selection of a

burst length, a burst type, a CAS latency, an operating mode and a write burst mode, as shown in Figure MODE

REGISTER DEFINITION. The mode register is programmed via the LOAD MODE REGISTER command and will

retain the stored information until it is programmed again or the device loses power.

Mode register bits M0 - M2 specify the burst length, M3 specifies the type of burst (sequential or interleaved), M4 -

M6 specify the CAS latency, M7 and M8 specify the operating mode, M9 specifies the WRITE burst mode, and M10,

M11, and M12 are reserved for future use.

The mode register must be loaded when all banks are idle, and the controller must wait the specified time before

initiating the subsequent operation. Violating either of these requirements will result in unspecified operation.