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IS67WVE1M16EBLL-70BLA1 Datasheet(PDF) 2 Page - Integrated Silicon Solution, Inc |
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IS67WVE1M16EBLL-70BLA1 Datasheet(HTML) 2 Page - Integrated Silicon Solution, Inc |
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2 / 34 page  2 IS66/67WVE1M16EALL/EBLL/ECLL IS66/67WVE1M16TALL/TBLL/TCLL Rev. C | Oct. 2015 www.issi.com - SRAM@issi.com General Description PSRAM products are high-speed, CMOS pseudo-static random access memory developed for low-power, portable applications. The 16Mb DRAM core device is organized as 1 Meg x 16 bits. These devices include the industry-standard, asynchronous memory interface found on other low-power SRAM or pseudo-SRAM (PSRAM) offerings. For seamless operation on an asynchronous memory bus, PSRAM products incorporated a transparent self-refresh mechanism. The hidden refresh requires no additional support from the system memory controller and has no significant impact on device read/write performance. A user-accessible configuration registers (CR) defines how the PSRAM device performs on- chip refresh and whether page mode read accesses are permitted. This register is automatically loaded with a default setting during power-up and can be updated at any time during normal operation. Special attention has been focused on current consumption during self-refresh. This product includes two system-accessible mechanisms to minimize refresh current. Setting sleep enable (ZZ#) to LOW enables one of two low-power modes: partial-array refresh (PAR) or deep power-down (DPD). PAR limits refresh to only that part of the DRAM array that contains essential data. DPD halts refresh operation altogether and is used when no vital information is stored in the device. The system-configurable refresh mechanisms are accessed through the CR. [ Functional Block Diagram] Address Decode Logic Configuration Register (CR) 1M X 16 DRAM Memory Array Input /Output Mux And Buffers DQ0~DQ15 A0~A19 Control Logic CE# WE# OE# LB# UB# ZZ# |
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