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SN75LVPE801 Datasheet(PDF) 7 Page - Texas Instruments |
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SN75LVPE801 Datasheet(HTML) 7 Page - Texas Instruments |
7 / 34 page 50mV IN+ Vcm IN- OUT+ Vcm OUT- t OOB2 t OOB1 tPDelay tPDelay IN OUT 7 SN75LVPE801 www.ti.com SLLSEW8 – SEPTEMBER 2016 Product Folder Links: SN75LVPE801 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated 7.6 Timing Requirements MIN TYP MAX UNIT DEVICE PARAMETERS tPDelay Propagation delay Measured using K28.5 pattern (see Figure 1) 275 350 ps AutoLPENTRY Auto low power entry time Electrical idle at input (see Figure 3) 11 μs AutoLPEXIT Auto low power exit time After first signal activity (see Figure 3) 33 50 ns OOB tOOB1 OOB mode enter See Figure 2 1 5 ns tOOB2 OOB mode exit See Figure 2 1 5 ns RECEIVER AC/DC t20-80RX Rise and fall time Rise times and fall times measured between 20% and 80% of the signal. SATA 8 Gbps speed measured 1" from device pin. 62 75 ps tskewRX Differential skew Difference between the single-ended mid-point of the RX+ signal rising and falling edge, and the single-ended mid- point of the RX– signal falling and rising edge. 30 ps TRANSMITTER AC/DC t20-80TX Rise and fall time Rise times and fall times measured between 20% and 80% of the signal. At 8 Gbps under no load conditions measured at the pin. 44 58 85 ps tskewTX Differential skew Difference between the single-ended mid-point of the TX+ signal rising edge and falling edge, and the single-ended mid-point of the TX– signal falling edge and rising edge, D1, D0 = VCC 2 15 ps txR/Flmb TX rise and fall imbalance At 8 Gbps 6% 20% txAmplmb TX amplitude imbalance 1% 10% TRANSMITTER JITTER Rise and Fall time 46.5 % 47.5 % 48.3 % Rise and Fall mismatch 1.5% 3% Figure 1. Propagation Delay Timing Diagram Figure 2. OOB Enter and Exit Timing |
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