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LM12L458 Datasheet(PDF) 4 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part # LM12L458
Description  12-Bit Sign Data Acquisition System with Self-Calibration
Download  36 Pages
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

LM12L458 Datasheet(HTML) 4 Page - National Semiconductor (TI)

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Converter Characteristics (Continued)
The following specifications apply for V
A+ = VD+ = 3.3V, VREF+ = 2.5V, VREF− = 0V, 12-bit + sign conversion mode, fCLK =
6.0 MHz, R
S = 25Ω, source impedance for VREF+ and VREF− ≤ 25Ω, fully-differential input with fixed 1.25V common-mode volt-
age, and minimum acquisition time unless otherwise specified. Boldface limits apply for T
A = TJ = TMIN to TMAX; all other
limits T
A = TJ = 25˚C. (Notes 6, 7, 8, 9)
Symbol
Parameter
Conditions
Typical
Limits
Unit
(Note 10)
(Note 11)
(Limit)
V
IN−
Inverting Input Range
GND
V (min)
V
A+
V (max)
V
IN+ −VIN−
Differential Input Voltage Range
−V
A
+
V (min)
V
A+
V (max)
Common Mode Input Voltage Range
GND
V (min)
V
A+
V (max)
PSS
Power Supply
Zero Error
V
A+ = VD+ = 3.3V ±10%
±0.2
±1.75
LSB (max)
Sensitivity
Full-Scale Error
V
REF+ = 2.5V, VREF− = GND
±0.4
±2
LSB (max)
(Note 15)
Linearity Error
±0.2
LSB
C
REF
V
REF+/VREF− Input Capacitance
85
pF
C
IN
Selected Multiplexer Channel Input
75
pF
Capacitance
Converter AC Characteristics
The following specifications apply for V
A+ = VD+ = 3.3V, VREF+ = 2.5V, VREF− = 0V, 12-bit + sign conversion mode, fCLK = 6.0
MHz, R
S = 25Ω, source impedance for VREF+ and VREF− ≤ 25Ω, fully-differential input with fixed 1.25V common-mode voltage,
and minimum acquisition time unless otherwise specified. Boldface limits apply for T
A = TJ = TMIN to TMAX; all other limits
T
A = TJ = 25˚C. (Notes 6, 7, 8, 9)
Symbol
Parameter
Conditions
Typical
Limits
Unit
(Note 10)
(Note 11)
(Limit)
Clock Duty Cycle
50
%
40
% (min)
60
% (max)
t
C
Conversion Time
13-Bit Resolution,
44 (t
CLK)
44 (t
CLK)+50ns
(max)
Sequencer State S5 (
Figure 15)
9-Bit Resolution,
21 (t
CLK)
21 (t
CLK)+50ns
(max)
Sequencer State S5 (
Figure 15)
t
A
Acquisition Time
Sequencer State S7 (
Figure 15)
9(t
CLK)
9(t
CLK)+50ns
(max)
Built-in minimum for 13-Bits
Built-in minimum for 9-Bits and
2(t
CLK)
2(t
CLK)+50ns
(max)
“Watchdog” mode
t
Z
Auto-Zero Time
Sequencer State S2 (
Figure 15)76 (t
CLK)
76 (t
CLK)+50ns
(max)
t
CAL
Full Calibration Time
Sequencer State S2 (
Figure 15)
4944 (t
CLK)
4944 (t
CLK)+50ns
(max)
Throughput Rate
107
106
kHz
(Note 18)
(min)
t
WD
“Watchdog” Mode
Sequencer States S6, S4,
11 (t
CLK)
11 (t
CLK)+50ns
(max)
Comparison Time
and S5 (
Figure 15)
t
PU
Power-Up Time
10
ms
t
WU
Wake-Up Time
10
ms
www.national.com
4


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