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LM12L458CIV Datasheet(PDF) 24 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part # LM12L458CIV
Description  12-Bit Sign Data Acquisition System with Self-Calibration
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

LM12L458CIV Datasheet(HTML) 24 Page - National Semiconductor (TI)

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2.0 Internal User-Programmable
Registers (Continued)
time the Sequencer retrieves and decodes Instruction 000.
The Sequencer generates INT 1 (by placing a “1” in the In-
terrupt Status register’s Bit 1) the second time and after the
Sequencer encounters Instruction 000. It is important to re-
member that the Sequencer continues to operate even if an
Instruction interrupt (INT 1) is internally or externally gener-
ated. The only mechanisms that stop the Sequencer are an
instruction with the PAUSE bit set to “1” (halts before instruc-
tion execution), placing a “0” in the Configuration register’s
START bit, or placing a “1” in the Configuration register’s RE-
SET bit.
Bits 11–15 hold the number of conversions that must be
stored in the Conversion FIFO in order to generate an inter-
nal interrupt. This internal interrupt appears in Bit 2 of the In-
terrupt Status register. If Bit 2 of the Interrupt Enable register
is set to “1”, an external interrupt will appear at pin 31 (INT).
2.5 INTERRUPT STATUS REGISTER
This read-only register is located at address 1010 (A4–A1,
BW = 0) or 1010x (A4–A0, BW = 1). The corresponding flag
in the Interrupt Status register goes high (“1”) any time that
an interrupt condition takes place, whether an interrupt is en-
abled or disabled in the Interrupt Enable register. Any of the
active (“1”) Interrupt Status register flags are reset to “0”
whenever this register is read or a device reset is issued
(see Bit 1 in the Configuration Register).
Bit 0 is set to “1” when a “watchdog” comparison limit inter-
rupt has taken place.
Bit 1 is set to “1” when the Sequencer has reached the ad-
dress stored in Bits 8–10 of the Interrupt Enable register.
Bit 2 is set to “1” when the Conversion FIFO’s limit, stored in
Bits 11–15 of the Interrupt Enable register, has been
reached.
Bit 3 is set to “1” when the single-sampled auto-zero has
been completed.
Bit 4 is set to “1” when an auto-zero and full linearity
self-calibration has been completed.
Bit 5 is set to “1” when a Pause interrupt has been gener-
ated.
Bit 6 is a “Don’t Care”.
Bit 7 is set to “1” when the LM12L458 return from
power-down to active mode.
Bits 8–10 hold the Sequencer’s actual instruction address
while it is running.
Bits 11–15 hold the actual number of conversions stored in
the Conversion FIFO while the Sequencer is running.
2.6 LIMIT STATUS REGISTER
The read-only register is located at address 1101 (A4–A1,
BW = 0) or 1101x (A4–A0, BW = 1). This register is used in
tandem with the Limit #1 and Limit #2 registers in the Instruc-
tion RAM. Whenever a given instruction’s input voltage ex-
ceeds the limit set in its corresponding Limit register (#1or
#2), a bit, corresponding to the instruction number, is set in
the Limit Status register. Any of the active (“1”) Limit Status
flags are reset to “0” whenever this register is read or a de-
vice reset is issued (see Bit 1 in the Configuration register).
This register holds the status of limits #1 and #2 for each of
the eight instructions.
Bits 0–7 show the Limit #1 status. Each bit will be set high
(“1”) when the corresponding instruction’s input voltage ex-
ceeds the threshold stored in the instruction’s Limit #1 regis-
ter. When, for example, instruction 3 is a “watchdog” opera-
tion (Bit 11 is set high) and the input for instruction 3 meets
the magnitude and/or polarity data stored in instruction 3’s
Limit #1 register, Bit 3 in the Limit Status register will be set
to a “1”.
Bits 8–15 show the Limit #2 status. Each bit will be set high
(“1”) when the corresponding instruction’s input voltage ex-
ceeds the threshold stored in the instruction’s Limit #2 regis-
ter. When, for example, the input to instruction 6 meets the
value stored in instruction 6’s Limit #2 register, Bit 14 in the
Limit Status register will be set to a “1”.
2.7 TIMER
The LM12L458 have an on-board 16-bit timer that includes a
5-bit pre-scaler. It uses the clock signal applied to pin 23 as
its input. It can generate time intervals of 0 through 2
21 clock
cycles in steps of 2
5. This time interval can be used to delay
the execution of instructions. It can also be used to slow the
conversion rate when converting slowly changing signals.
This can reduce the amount of redundant data stored in the
FIFO and retrieved by the controller.
The user-defined timing value used by the Timer is stored in
the 16-bit READ/WRITE Timer register at location 1011
(A4–A1, BW = 0) or 1011x (A4–A0, BW = 1) and is
pre-loaded automatically. Bits 0–7 hold the preset value’s
low byte and Bits 8–15 hold the high byte. The Timer is ac-
tivated by the Sequencer only if the current instruction’s Bit 9
is set (“1”). If the equivalent decimal value “N” (0
≤ N ≤ 216
1) is written inside the 16-bit Timer register and the Timer is
enabled by setting an instruction’s bit 9 to a “1”, the Se-
quencer will delay the same instruction’s execution by halt-
ing at state 3 (S3), as shown in
Figure 15, for 32 x N + 2
clock cycles.
2.8 DMA
The DMA works in tandem with Interrupt 2. An active DMA
Request on pin 32 (DMARQ) requires that the FIFO interrupt
be enabled. The voltage on the DMARQ pin goes high when
the number of conversions in the FIFO equals the 5-bit value
stored in the Interrupt Enable register (bits 11–15). The volt-
age on the INT pin goes low at the same time as the voltage
on the DMARQ pin goes high. The voltage on the DMARQ
pin goes low when the FIFO is emptied. The Interrupt Status
register must be read to clear the FIFO interrupt flag in order
to enable the next DMA request.
DMA operation is optimized through the use of the 16-bit
databus connection (a logic “0” applied to the BW pin). Using
this bus width allows DMA controllers that have single ad-
dress Read/Write capability to easily unload the FIFO. Using
DMA on an 8-bit databus is more difficult. Two read opera-
tions (low byte, high byte) are needed to retrieve each con-
version result from the FIFO. Therefore, the DMA controller
must be able to repeatedly access two constant addresses
when transferring data from the LM12L458 to the host sys-
tem.
3.0 FIFO
The result of each conversion stored in an internal read-only
FIFO (First-In, First-Out) register. It is located at 1100
(A4–A1, BW = 0) or 1100x (A4–A0, BW = 1). This register
has 32 16-bit wide locations. Each location holds 13-bit data.
Bits 0–3 hold the four LSB’s in the 12 bits + sign mode or
“1110” in the 8 bits + sign mode. Bits 4–11 hold the eight
MSB’s and Bit 12 holds the sign bit. Bits 13–15 can hold ei-
ther the sign bit, extending the register’s two’s complement
www.national.com
24


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