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LM12L458CIV Datasheet(PDF) 27 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part # LM12L458CIV
Description  12-Bit Sign Data Acquisition System with Self-Calibration
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
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LM12L458CIV Datasheet(HTML) 27 Page - National Semiconductor (TI)

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5.0 Analog Considerations
5.1 REFERENCE VOLTAGE
The difference in the voltages applied to the V
REF+ and
V
REF− defines the analog input voltage span (the difference
between the voltages applied between two multiplexer inputs
or the voltage applied to one of the multiplexer inputs and
analog ground), over which 4095 positive and 4096 negative
codes exist. The voltage sources driving V
REF+ or VREF−
must have very low output impedance and noise.
The ADC can be used in either ratiometric or absolute refer-
ence applications. In ratiometric systems, the analog input
voltage is proportional to the voltage used for the ADC’s ref-
erence voltage. When this voltage is the system power sup-
ply, the V
REF+ pin is connected to VA+ and VREF− is con-
nected to GND. This technique relaxes the system reference
stability requirements because the analog input voltage and
the ADC reference voltage move together. This maintains
the same output code for given input conditions.
For absolute accuracy, where the analog input voltage varies
between very specific voltage limits, a time and temperature
stable voltage source can be connected to the reference in-
puts. Typically, the reference voltage’s magnitude will require
an initial adjustment to null reference voltage induced
full-scale errors.
5.2 INPUT RANGE
The LM12L458’s fully differential ADC and reference voltage
inputs generate a two’s-complement output that is found by
using the equation below.
Round up to the next integer value between −4096 to 4095
for 12-bit resolution and between −256 to 255 for 8-bit reso-
lution if the result of the above equation is not a whole num-
ber. As an example, V
REF+ = 2.5V, VREF− = 1V, VIN+ = 1.5V
and V
IN− = GND. The 12-bit + sign output code is positive
full-scale, or 0,1111,1111,1111. If V
REF+ = 3.3V, VREF− = 1V,
V
IN+ = 3V, and VIN− = GND, the 12-bit + sign output code is
0,1100,0000,0000.
5.3 INPUT CURRENT
A charging current flows into or out of (depending on the in-
put voltage polarity) the analog input pins, IN0–IN7 at the
start of the analog input acquisition time (t
ACQ). This cur-
rent’s peak value will depend on the actual input voltage ap-
plied.
5.4 INPUT SOURCE RESISTANCE
For low impedance voltage sources (<80
Ω for 6 MHz opera-
tion) the input charging current will decay, before the end of
the S/H’s acquisition time, to a value that will not introduce
any conversion errors. For higher source impedances, the
S/H’s acquisition time can be increased. As an example, op-
erating with a 6 MHz clock frequency and maximum acquisi-
tion time, the LM12L458’s analog inputs can handle source
impedance as high as 5.56 k
Ω. Refer to Section 2.1, Instruc-
tion RAM “00”, Bits 12–15 for further information.
5.5 INPUT BYPASS CAPACITANCE
External capacitors (0.01 µF–0.1 µF) can be connected be-
tween the analog input pins, IN0–IN7, and analog ground to
filter any noise caused by inductive pickup associated with
long input leads. It will not degrade the conversion accuracy.
5.6 NOISE
The leads to each of the analog multiplexer input pins should
be kept as short as possible. This will minimize input noise
and clock frequency coupling that can cause conversion er-
rors. Input filtering can be used to reduce the effects of the
noise sources.
5.7 POWER SUPPLIES
Noise spikes on the V
A+ and VD+ supply lines can cause
conversion errors; the comparator will respond to the noise.
The ADC is especially sensitive to any power supply spikes
that occur during the auto-zero or linearity correction. Low in-
ductance tantalum capacitors of 10 µF or greater paralleled
with 0.1 µF monolithic ceramic capacitors are recommended
for supply bypassing. Separate bypass capacitors should be
used for the V
A+ and VD+ supplies and placed as close as
possible to these pins.
5.8 GROUNDING
The LM12L458’s nominal high resolution performance can
be maximized through proper grounding techniques. These
include the use of separate analog and digital ground
planes. The digital ground plane is placed under all compo-
nents that handle digital signals, while the analog ground
plane is placed under all analog signal handling circuitry. The
digital and analog ground planes are connected at only one
point, the power supply ground. This greatly reduces the oc-
currence of ground loops and noise.
It is recommended that stray capacitance between the ana-
log inputs (IN0–IN7, V
REF+, and VREF−) be reduced by in-
creasing the clearance (+1/16th inch) between the analog
signal and reference pins and the ground plane.
5.9 CLOCK SIGNAL LINE ISOLATION
The LM12L458’s performance is optimized by routing the
analog input/output and reference signal conductors (pins
34–44) as far as possible from the conductor that carries the
clock signal to pin 23. Ground traces parallel to the clock sig-
nal trace can be used on printed circuit boards to reduce
clock signal interference on the analog input/output pins.
6.0 Application Circuits
6.1 PC EVALUATION/INTERFACE BOARD
Figure 16 is the schematic of an evaluation/interface board
designed to interface the LM12454 or LM12(H)458 with an
XT or AT® style computer. The LM12(H)454/8 is the 5V ver-
sion of the Data Acquisition System. It is functionally equiva-
lent to the LM12L458. See the LM12(H)454/8 datasheet for
further information. The board can be used to develop both
software and hardware for applications using the LM12L458.
The board hardwires the BW (Bus Width) pin to a logic high,
selecting an 8-bit wide databus. Therefore, it is designed for
an 8-bit expansion slot on the computer’s motherboard.
The circuit operates on a single +5V supply derived from the
computer’s +12V supply using an LM340 regulator. This
www.national.com
27


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