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LM12L458CIV Datasheet(PDF) 28 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part # LM12L458CIV
Description  12-Bit Sign Data Acquisition System with Self-Calibration
Download  36 Pages
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

LM12L458CIV Datasheet(HTML) 28 Page - National Semiconductor (TI)

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6.0 Application Circuits (Continued)
greatly attenuates noise that may be present on the comput-
er’s power supply lines. However, your application may only
need an LC filter.
Figure 16 also shows the recommended supply (V
A+ and
V
D+) and reference input (VREF+ and VREF−) bypassing. The
digital and analog supply pins can be connected together to
the same supply voltage. However, they need separate, mul-
tiple bypass capacitors. Multiple capacitors on the supply
pins and the reference inputs ensures a low impedance by-
pass path over a wide frequency range.
All digital interface control signals (IOR, IOW, and AEN),
data lines (DB0–DB7), address lines (A0–A9), and IRQ (in-
terrupt request) lines (IRQ2, IRQ3, and IRQ5) connections
are made through the motherboard slot connector. All analog
signals applied to, or received by, the input multiplexer
(IN0–IN7 for the LM12(H)458 and IN0–IN3, MUXOUT+,
MUXOUT−, S/H IN+ and S/H IN− for the LM12454), V
REF+,
V
REF−,VREFOUT, and the SYNC signal input/ output are ap-
plied through a DB-37 connector on the rear side of the
board.
Figure 16 shows that there are numerous analog
ground connections available on the DB-37 connector.
The voltage applied to V
REF− and VREF+ is selected using
two jumpers, JP1 and JP2. JP1 selects between the voltage
applied to the DB-37’s pin 24 or GND and applies it to the
LM12(H)454/8’s V
REF−
input. JP2 selects between the
LM12(H)454/8’s internal reference output, V
REFOUT, and the
voltage applied to the DB-37’s pin 22 and applies it to the
LM12(H)454/8’s V
REF+ input.
TABLE 2. LM12(H)454/8 Evaluation/Interface
Board SW DIP-8 Switch Settings
for Available I/O Memory Locations
Hexidecimal
SW DIP-8
I/O Memory
Base
SW1
SW2
SW3
SW4
Address
(SEL0)
(SEL1)
(SEL2)
(SEL3)
100
ON
ON
ON
ON
120
OFF
ON
ON
ON
Hexidecimal
SW DIP-8
I/O Memory
Base
SW1
SW2
SW3
SW4
Address
(SEL0)
(SEL1)
(SEL2)
(SEL3)
140
ON
OFF
ON
ON
160
OFF
OFF
ON
ON
180
ON
ON
OFF
ON
1A0
OFF
ON
OFF
ON
1C0
ON
OFF
OFF
ON
300
OFF
OFF
OFF
ON
340
ON
ON
ON
OFF
280
OFF
ON
ON
OFF
2A0
ON
OFF
ON
OFF
The board allows the use of one of three Interrupt Request
(IRQ) lines IRQ2, IRQ3, and IRQ5. The individual IRQ line
can be selected using switches 5, 6, and 7 of SW DIP-8.
When using any of these three IRQs, the user needs to en-
sure that there are no conflicts between the evaluation board
and any other boards attached to the computer’s mother-
board.
Switches 1–4, along with address lines A5–A9 are used as
inputs to GAL16V8 Programmable Gate Array (U2). This de-
vice forms the interface between the computer’s control and
address lines and generates the control signals used by the
LM12(H)454/8 for CS, WR, and RD. It also generates the
signal that controls the data buffers. Several address ranges
within the computer’s I/O memory map are available. Refer
to
Table 2 for the switch settings that gives the desired I/O
memory address range. Selection of an address range must
be done so that there are no conflicts between the evaluation
board and any other boards attached to the computer’s
motherboard. The GAL equations are shown in
Figure 17.
The GAL functional block diagram is shown in
Figure 18.
Figures 19, 20, 21, 22 show the layout of each layer in the
3-layer evaluation/interface board plus the silk-screen layout
showing parts placement.
Figure 20 is the top or component
side,
Figure 21 is the middle or ground plane layer, Figure 22
is the circuit side, and
Figure 19 is the parts layout.
www.national.com
28


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