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TAS5036 Datasheet(PDF) 5 Page - Texas Instruments |
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TAS5036 Datasheet(HTML) 5 Page - Texas Instruments |
5 / 49 page List of Tables 5 November 2002 SLES044B 5–5 Mute Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5–6 Right-Justified, IIS, Left-Justified Serial Protocol Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5–7 Right, Left, and IIS Serial Mode Timing Requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5–8 Serial Audio Ports Master Mode Timing . . . . . . . 35 5–9 DSP Serial Port Timing . . . . . . . . . . . . . . . . . . . . . 35 5–10 DSP Serial Port Expanded Timing . . . . . . . . . . . 36 5–11 DSP Absolute Timing . . . . . . . . . . . . . . . . . . . . . . 36 5–12 SCL and SDA Timing . . . . . . . . . . . . . . . . . . . . . . 37 5–13 Start and Stop Conditions Timing . . . . . . . . . . . . 37 6–1 Typical TAS5036 Application . . . . . . . . . . . . . . . . . 38 6–2 TAS5036 Serial Audio Port—Slave Mode Connection Diagram . . . . . . . . . . . . . . . . . . . . . 39 6–3 TAS5036 Serial Audio Port—Master Mode Connection Diagram . . . . . . . . . . . . . . . . . . . . . 39 List of Tables Table Title Page 2–1 Normal-Speed, Double-Speed, and Quad-Speed Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2–2 Master and Slave Clock Modes . . . . . . . . . . . . . . 9 2–3 LRCLK, MCLK_IN, and External PLL Rates . . . 9 2–4 DCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2–5 Supported Word Lengths . . . . . . . . . . . . . . . . . . . . 11 2–6 Device Outputs During Reset . . . . . . . . . . . . . . . . 15 2–7 Values Set During Reset . . . . . . . . . . . . . . . . . . . . 15 2–8 Device Outputs During Power Down . . . . . . . . . . 16 2–9 Volume Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2–10 De-Emphasis Filter Characteristics . . . . . . . . . . 18 2–11 Device Outputs During Error Recovery . . . . . . . 20 3–1 I2C Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3–2 General Status Register (Read Only) . . . . . . . . . 25 3–3 Error Status Register . . . . . . . . . . . . . . . . . . . . . . . 25 3–4 System Control Register 0 . . . . . . . . . . . . . . . . . . 25 3–5 System Control Register 1 . . . . . . . . . . . . . . . . . . 26 3–6 Error Recovery Register . . . . . . . . . . . . . . . . . . . . 26 3–7 Automute Delay Register . . . . . . . . . . . . . . . . . . . . 26 3–8 DC-Offset Control Registers . . . . . . . . . . . . . . . . . 27 3–9 Six Inter-Channel Delay Registers . . . . . . . . . . . . 27 3–10 ABD Delay Register . . . . . . . . . . . . . . . . . . . . . . . 27 3–11 Individual Channel Mute Register . . . . . . . . . . . . 27 |
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