Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

TMS416400, TMS416400P, TMS417400, TMS417400P

TMS426400, TMS426400P, TMS427400, TMS427400P

4194304-WORD BY 4-BIT HIGH-SPEED DRAMS

SMKS881B – MAY 1995 – REVISED AUGUST 1995

1

POST OFFICE BOX 1443

Electrical characteristics for TMS416400 / P and

TMS417400 / P is Production Data. Electrical

characteristics

for

TMS426400 / P

and

TMS427400 / P is Product Preview only.

(

±10% Tolerance)

TMS42x400 / P (

±0.3 V Tolerance)

ACCESS ACCESS ACCESS READ OR

TIME

TIME

TIME

WRITE

tRAC

tCAC

tAA

CYCLE

MAX

MAX

MAX

MIN

’4xx400/P-60

60 ns

15 ns

30 ns

110 ns

’4xx400/P-70

70 ns

18 ns

35 ns

130 ns

’4xx400/P-80

80 ns

20 ns

40 ns

150 ns

CAS-Before-RAS ( CBR ) Refresh

Option ( TMS4xx400P)

300-Mil-Wide Surface-Mount Small-Outline

J-Lead (SOJ) Package and 24 / 26-Lead

Surface-Mount Thin Small-Outline Package

( TSOP)

0

°C to 70°C

CMOS) Technology

AVAILABLE OPTIONS

DEVICE

POWER

SUPPLY

SELF

REFRESH

BATTERY

BACKUP

REFRESH

CYCLES

TMS416400

TMS416400P

TMS417400

TMS417400P

TMS426400

TMS426400P

TMS427400

TMS427400P

5 V

5 V

5 V

5 V

3.3 V

3.3 V

3.3 V

3.3 V

—

Yes

—

Yes

—

Yes

—

Yes

4096 in 64 ms

4096 in 128 ms

2048 in 32 ms

2048 in 128 ms

4096 in 64 ms

4096 in 128 ms

2048 in 32 ms

2048 in 128 ms

These devices feature maximum RAS access times of 60 ns, 70 ns, and 80 ns. All addresses and data-in lines

are latched on-chip to simplify system design. Data out is unlatched to allow greater system flexibility.

‡ See Available Options Table

PIN NOMENCLATURE

A0 – A11†

Address Inputs

CAS

Column-Address Strobe

DQ1 – DQ4

Data In / Data Out

OE

Output Enable

NC

No Internal Connection

RAS

Row-Address Strobe

VCC

5-V or 3.3-V Supply‡

VSS

Ground

W

Write Enable

DJ PACKAGE

( TOP VIEW )

DQ1

DQ2

W

RAS

A0

A1

A2

A3

DQ4

DQ3

CAS

OE

A7

A6

A5

A4

26

25

24

23

22

18

17

16

15

14

1

2

3

4

5

9

10

11

12

13

A9

21

6

A10

A8

19

8

DGA PACKAGE

( TOP VIEW )

DQ1

DQ2

W

RAS

A0

A1

A2

A3

DQ4

DQ3

CAS

OE

A7

A6

A5

A4

26

25

24

23

22

18

17

16

15

14

1

2

3

4

5

9

10

11

12

13

A9

21

6

A10

A8

19

8

† A11 is NC for TMS4x7400 / P.

description

The

TMS4xx400

is

a

set

of

high-speed,

16 777 216-bit dynamic random-access memories

organized as 4 194 304 words of 4 bits each. The

TMS4xx400P series are high-speed, low-power,

self-refresh,

16 777 216-bit

dynamic

random-

access memories organized as 4 194 304 words of

4 bits each. The TMS4xx400 and TMS4xx400P

employ

state-of-the-art

EPIC

™

(Enhanced

Performance Implanted CMOS) technology for

high performance, reliability, and low power.

UNLESS OTHERWISE NOTED this document contains PRODUCTION

DATA information current as of publication date. Products conform to

specifications per the terms of Texas Instruments standard warranty.

Production processing does not necessarily include testing of all

parameters.

Copyright

© 1995, Texas Instruments Incorporated

EPIC is a trademark of Texas Instruments Incorporated.