ADS5204

SBAS268A – JUNE 2002 – REVISED JULY 2002

www.ti.com

3

ELECTRICAL CHARACTERISTICS

over recommended operating conditions with fCLK = 80MHz and use of internal voltage references, and PGA Gain = 0dB, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Power Supply

AVDD

AV

DV

DRV

3 3V

64

72

IDD Operating Supply Current

DVDD

AVDD = DVDD = DRVDD = 3.3V,

CL =10pFVIN = 3 5MHz –1dBFS

1.7

2.2

mA

IDD O erating Su ly Current

DRVDD

CL = 10pF, VIN = 3.5MHz, –1dBFS

18

27

mA

Power Dissipation

PD

PWDN_REF = ‘L’

275

345

mW

Power Dissipation

PD

PWDN_REF = ‘H’

240

300

mW

Standby Power

PD(STBY)

STDBY = ‘H’, CLK Held HIGH or LOW

95

150

µW

Power-Up Time for All References from Standby

tPD

550

ms

Wake Up Time

tWU

External Reference

40

µs

Digital Inputs

High-Level Input Current on Digital Inputs incl. CLK

IIH

AVDD =DVDD =DRVDD =36V

–1

+1

µA

Low-Level Input Current on Digital Inputs incl. CLK

IIL

AVDD = DVDD = DRVDD = 3.6V

–1

+1

µA

Digital Outputs

High-Level Output Voltage

VOH

AVDD = DVDD = DRVDD = 3.0V at

IOH = 50µA, Digital Outputs Forced HIGH

2.8

2.96

V

Low-Level Output Voltage

VOL

AVDD = DVDD = DRVDD = 3.0V at

IOL = 50µA, Digital Outputs Forced LOW

0.04

0.2

V

Output Capacitance

CO

5

pF

High-Impedance State Output Current to High–Level

IOZH

AVDD =DVDD =DRVDD =36V

–1

+1

µA

High-Impedance State Output Current to Low–Level

IOZL

AVDD = DVDD = DRVDD = 3.6V

–1

+1

µA

Data Output Rise and Fall Time

CLOAD = 10pF, Single-Bus Mode

3

ns

Data Output Rise-and-Fall Time

CLOAD = 10pF, Dual-Bus Mode

5

ns

Reference Outputs

Reference Top Voltage

VREFTO

Absolute Min/Max Values Valid and

1.9

2

2.1

V

Reference Bottom Voltage

VREFBO

Absolute Min/Max Values Valid and

Tested for AVDD = 3.3V

0.95

1

1.05

V

Differential Reference Votage

REFT – REFB

0.95

1.0

1.05

V

DC Accuracy

Integral Nonlinearity End Point

INL

Internal

TA = 40°C to +85°C

15

±04

+1 5

LSB

Integral Nonlinearity, End Point

INL

Internal

References(1)

TA = –40°C to +85°C

–1.5

±0.4

+1.5

LSB

Differential Nonlinearity

DNL

Internal

References(2)

TA = –40°C to +85°C

–0.9

±0.4

+1.0

LSB

Missing Codes

No Missing Codes Assured

Zero Error(3)

AV

DV

DRV

3 3V

0.12

±1.5

%FS

Full-Scale Error

AVDD = DVDD = DRVDD = 3.3V

External References (3)

0.28

±1.5

%FS

Gain Error

External References (3)

0.24

±1.5

%FS

(1) Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero to full-scale. The point used as zero occurs ½LSB

before the first code transition. The full-scale point is defined as a level

½LSB beyond the last code transition. The deviation is measured from

the center of each particular code to the best-fit line between these two endpoints.

(2) An ideal ADC exhibits code transitions that are exactly 1LSB apart. DNL is the deviation from this ideal value. Therefore this measure indicates

how uniform the transfer function step sizes are. The ideal step size is defined here as the step size for the device under test, (i.e., (last transition

level – first transition level)/(2n – 2)). Using this definition for DNL separates the effects of gain and offset error. A minimum DNL better than

–1LSB ensures no missing codes.

(3) Zero error is defined as the difference in analog input voltage—between the ideal voltage and the actual voltage—that will switch the ADC output

from code 0 to code 1. The ideal voltage level is determined by adding the voltage corresponding to

½LSB to the bottom reference level. The

voltage corresponding to 1LSB is found from the difference of top and bottom references divided by the number of ADC output levels (1024).

Full-scale error is defined as the difference in analog input voltage—between the ideal voltage and the actual voltage—that will switch the ADC

output from code 1022 to code 1023. The ideal voltage level is determined by subtracting the voltage corresponding to 1.5LSB from the top

reference level. The voltage corresponding to 1LSB is found from the difference of top and bottom references divided by the number of ADC

output levels (1024).