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TAS6424-Q1 Datasheet(PDF) 10 Page - Texas Instruments |
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TAS6424-Q1 Datasheet(HTML) 10 Page - Texas Instruments |
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10 / 68 page  10 TAS6424-Q1 SLOS870A – SEPTEMBER 2016 – REVISED OCTOBER 2016 www.ti.com Product Folder Links: TAS6424-Q1 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated 7.6 Timing Requirements Test conditions (unless otherwise noted): TC = 25°C, PVDD = VBAT = 14.4 V, VDD = 3.3 V, RL = 4 Ω, PO = 1 W/ch, ƒ = 1 kHz, fSW = 2.11 MHz, AES17 Filter, default I 2C settings, see Figure 79 and Figure 82 MIN NOM MAX UNIT I2C CONTROL PORT (See Figure 42) tBUS Bus free time between start and stop conditions 1.3 μs tHOLD1 Hold time, SCL to SDA 0 ns tHOLD2 Hold time, start condition to SCL 0.6 μs tSTART I2C startup time after VDD power on reset 12 ms tRISE Rise time, SCL and SDA 300 ns tFALL Fall time, SCL and SDA 300 ns tSU1 Setup, SDA to SCL 100 ns tSU2 Setup, SCL to start condition 0.6 μs tSU3 Setup, SCL to stop condition 0.6 μs tW(H) Required pulse duration SCL High 0.6 μs tW(L) Required pulse duration SCL Low 1.3 μs SERIAL AUDIO PORT (See Figure 36) DMCLK, DSCLK Allowable input clock duty cycle 45% 50% 55% ƒMCLK Supported MCLK frequencies: 128, 256, or 512 128 512 xFS ƒMCLK_Max Maximum frequency 25 MHz tSCY SCLK pulse cycle time 40 ns tSCL SCLK pulse-with LOW 16 ns tSCH SCLK pulse-with HIGH 16 ns trise/fall Rise and fall time 4 ns tSF SCLK rising edge to FSYNC edge 8 ns tFS FSYNC rising edge to SCLK edge 8 ns tDS DATA set-up time 8 ns tDH DATA hold time 8 ns ci Input capacitance, pins MCLK, SCLK, FSYNC, SDIN1, SDIN2 10 pF TLA Latency from input to output measured in FSYNC sample count FSYNC = 44.1 kHz or 48 kHz 30 FSYNC = 96 kHz 12 |
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