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BD39002EFV-CE2 Datasheet(PDF) 11 Page - Rohm

Part # BD39002EFV-CE2
Description  Buck-Boost Switching Regulator Watch Dog Timer
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Manufacturer  ROHM [Rohm]
Direct Link  http://www.rohm.com
Logo ROHM - Rohm

BD39002EFV-CE2 Datasheet(HTML) 11 Page - Rohm

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Datasheet
Datasheet
BD39002EFV-C
© 2014 ROHM Co., Ltd. All rights reserved.
www.rohm.com
TSZ22111・15・001
TSZ02201-0T2T0AM00200-1-2
Oct.29.2014 Rev.001
Description of Blocks
Under Voltage Lockout circuit (VCC_UVLO)
This is a Low Voltage Error Prevention Circuit.
In case of SEL_UVLO = OPEN, if the VCC drops below 3.6 V (Typ), the VCC_UVLO is activated and the output circuit
shuts down. In case of SEL_UVLO = GND, if the VCC drops below 5.58 V (Typ), the VCC_UVLO is activated and the
output circuit shuts down.
Thermal Shut Down (TSD)
The TSD protects the device from overheating.
If the chip temperature (Tj) reaches 175 °C (Typ), the circuit shuts down
Over Voltage Detection (OVD)
If DC / DC1 and LDO output voltage exceeds OVD, each PGOOD Pin turns Low.
DC / DC1 OVD monitors FB1 voltage and LDO OVD monitors VO2 voltage.
PGOOD pin is an open drain output and a pull up resistor should be connected to PGOOD if this function is being used.
Low Voltage Detection (LVD)
If DC / DC1 and LDO output voltage is below LVD, each PGOOD Pin turns Low.
DC / DC1 LVD monitors FB1 voltage and LDO LVD monitors VO2 voltage.
PGOOD pin is an open drain output, and a pull up resistor should be connected to PGOOD if this function is being used.
Over Current Protection (OCP)
DC / DC1 has two levels over current protection with different control system as shown below.
1) OCP1 low level operations (OCP1_L)
In case the voltage between VCC and CL exceeds 100 mV (Typ), OCP1 (low level operation) is activated and the
switching pulse width of OUTH and the switching pulse width of OUTL are limited. Also, if this pulse limited status
continues during 256 clock times where the FB1 pin voltage drops below the under voltage detection level, the soft
start pin capacitor is discharged and the output is turned OFF during 8192 clock times.
During the 8192 clock in which the output is turned OFF, the logic of OUTH and OUTL pin changes as follows;
OUTH = H and OUTL = H. After the 8192 clock the chip returns to normal operations and the soft start pin is
recharged.
2) OCP1 high level operations (OCP1_H)
In case the inter VCC - CL pin voltage exceeds 200 mV (Typ), the chip goes into OCP1 high level operations, the
soft start pin capacitor is discharged and the output is turned OFF for 8192 clk. During the 8192 clock in which the
output is turned OFF, the logic of OUTH and OUTL pin changes as follows; OUTH = H and OUTL = H. After the
8192 clock the chip returns to normal operations and the soft start pin is recharged.
Figure 15. Timing chart for DC / DC1 protection
・If the output current of LDO exceed OCP, the output current is limited and the output voltage is lowered.
CL
FB1
ISW
PG1
SS1
OUTH
OUTL
256clk
8192clk
OVP
UVP
8192clk
VO1
OCP LOW level operation
OCP High level
operation
OCP LOW level operation
Discharge SS
OUTH=High,OUTL=High
fix to logic
Normal operation
Normal operation
OUTH=High,OUTL=High
fix to logic
Output pulse is limited
Discharge SS


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