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OPT3006YMFR Datasheet(PDF) 6 Page - Texas Instruments

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Part # OPT3006YMFR
Description  OPT3006 Ultra-Thin Ambient Light Sensor
Download  41 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

OPT3006YMFR Datasheet(HTML) 6 Page - Texas Instruments

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tFC
SCL
SDA
tLOW
Stop
70%
30%
70%
30%
tRC
tSUSTA
tHDSTA
tSUSTO
tHIGH
tFD
tRD
tBUF
1/fSCL
tSUDAT
tHDDAT
Start
Start
Stop
6
OPT3006
SBOS698 – OCTOBER 2016
www.ti.com
Product Folder Links: OPT3006
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
(1)
All timing parameters are referenced to low and high voltage thresholds of 30% and 70%, respectively, of final settled value.
6.6 Timing Requirements
(1)
MIN
TYP
MAX
UNIT
I2C FAST MODE
fSCL
SCL operating frequency
0.01
0.4
MHz
tBUF
Bus free time between stop and start
1300
ns
tHDSTA
Hold time after repeated start
600
ns
tSUSTA
Setup time for repeated start
600
ns
tSUSTO
Setup time for stop
600
ns
tHDDAT
Data hold time
20
900
ns
tSUDAT
Data setup time
100
ns
tLOW
SCL clock low period
1300
ns
tHIGH
SCL clock high period
600
ns
tRC and tFC
Clock rise and fall time
300
ns
tRD and tFD
Data rise and fall time
300
ns
tTIMEO
Bus timeout period. If the SCL line is held low for this duration of time, the bus
state machine is reset.
28
ms
I2C HIGH-SPEED MODE
fSCL
SCL operating frequency
0.01
2.6
MHz
tBUF
Bus free time between stop and start
160
ns
tHDSTA
Hold time after repeated start
160
ns
tSUSTA
Setup time for repeated start
160
ns
tSUSTO
Setup time for stop
160
ns
tHDDAT
Data hold time
20
140
ns
tSUDAT
Data setup time
20
ns
tLOW
SCL clock low period
240
ns
tHIGH
SCL clock high period
60
ns
tRC and tFC
Clock rise and fall time
40
ns
tRD and tFD
Data rise and fall time
80
ns
tTIMEO
Bus timeout period. If the SCL line is held low for this duration of time, the bus
state machine is reset.
28
ms
Figure 1. I2C Detailed Timing Diagram


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