1A

1Y

1OE

1

2

6

2A

2OE

7

5

3

2Y

SN74LVC2G126-EP

SCES856 – DECEMBER 2013

www.ti.com

Logic Diagram (Positive Logic)

ABSOLUTE MAXIMUM RATINGs

(1)

over operating free-air temperature range (unless otherwise noted)

MIN

MAX

UNIT

Supply voltage range

–0.5

6.5

V

–0.5

6.5

V

–0.5

6.5

V

–0.5

V

Input clamp current

–50

mA

Output clamp current

–50

mA

Continuous output current

±50

mA

±100

mA

Absolute maximum junction temperature range

–55

150

°C

Storage temperature range

–65

150

°C

(1)

Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating

conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2)

The input negative-voltage and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

(3)

THERMAL INFORMATION

SN74LVC2G126-EP

DCU

UNITS

8 PINS

204.3

78

83

°C/W

7.6

82.6

N/A

(1)

For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2)

The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(3)

The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-

standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(4)

The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

(5)

The junction-to-top characterization parameter,

from the simulation data for obtaining

(6)

The junction-to-board characterization parameter,

from the simulation data for obtaining

(7)

The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific

JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

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