D1U54-D-650-12-HBxC Series

54mm 1U Front End DC-DC Power Supply Converter

D1U54-D-650-12-HBxC.A02 Page 4 of 9

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STATUS AND CONTROL SIGNALS

Signal Name

I/O

Description

Interface Details

INPUT_OK (DC Source)

Output

The signal output is driven high when the input source is available and within acceptable limits.

The output is driven low to indicate loss of input power.

There is a minimum of 5ms pre-warning time before signal changes to a high impedance state or

is driven low to indicate loss of 12V. The power supply must ensure that this interface signal

provides accurate status when DC power is lost.

Pulled up internally via 10K to 3.3Vdc.

A logic high >2.0Vdc; A logic low <0.8Vdc

Driven low by internal CMOS buffer (open

drain output).

PW_OK (Output OK)

Output

The signal is asserted, driven high, by the power supply to indicate that all outputs are valid. If any

of the outputs fail then this output will be hi-Z or driven low. The output is driven low to indicate

that the Main output is outside of lower limit of regulation.

Pulled up internally via 10K to 3.3Vdc.

A logic high >2.0Vdc; A logic low <0.8Vdc

Driven low by internal CMOS buffer (open

drain output).

SMB_ALERT

(FAULT/WARNING)

Output

The signal output is driven low to indicate that the power supply has detected a warning or fault

and is intended to alert the system. This output must be driven high when the power is operating

correctly (within specified limits).

The signal will revert to a high level when the warning/fault stimulus (that caused the alert) is

removed.

Pulled up internally via 10K to 3.3Vdc.

A logic high >2.0Vdc;A logic low <0.8Vdc

Driven low by internal CMOS buffer (open

drain output).

PRESENT_L

(Power Supply Absent)

Output

The signal is used to detect the presence (installed) of a PSU by the host system. The signal is

connected to PSU logic SGND within the power module.

Passive connection to +VSB_Return.

A logic low <0.8Vdc

PS_ON

(Power Supply

Enable/Disable

Input

This signal is pulled up internally to the internal housekeeping supply (within the power supply).

The power supply main 12Vdc output will be enabled when this signal is pulled low to

+VSB_Return.

In the low state the signal input shall not source more than 1mA of current. The 12Vdc output will

be disabled when the input is driven higher than 2.4V, or open circuited. Cycling this signal shall

clear latched fault conditions.

Pulled up internally via 10K to 3.3Vdc.

A logic high >2.0Vdc

A logic low <0.8Vdc

Input is via CMOS Schmitt trigger buffer.

PS_KILL

Input

This signal is used during hot swap to disable the main output during hot swap extraction. The

input is pulled up internally to the internal housekeeping supply (within the power supply).

The signal is provided on a short (lagging pin) and should be connected to +VSB_Return.

Pulled up internally via 10K to 3.3Vdc.

A logic high >2.0Vdc; A logic low <0.8Vdc

Input is via CMOS Schmitt trigger buffer.

ADDR (Address Select)

Input

An analogue input that is used to set the address of the internal slave devices (EEPROM and

microprocessor) used for digital communications.

Connection of a suitable resistor to +VSB_Return, in conjunction with an internal resistor divider

chain, will configure the required address (see ADDR Address Selection table).

DC voltage between the limits of 0 and

+3.3Vdc.

SCL (Serial Clock)

Both

Requirements Rev 1.1.

No additional internal capacitance is added that would affect the speed of the bus.

The signal is provided with a series isolator device to disconnect the internal power supply bus in

the event that the power module is completely unpowered,

SDA (Serial Data)

Both

Requirements Rev 1.1.

The signal is provided with a series isolator device to disconnect the internal power supply bus in

the event that the power module is completely unpowered,

V1_SENSE

V1SENSE_RTN

Input

Remote sense connections intended to be connected at and sense the voltage at the point of load.

The voltage sense will interact with the internal module regulation loop to compensate for voltage

drops due to connection resistance between the output connector and the load.

If remote sense compensation is not required then the voltage shall be configured for local sense

by:

1. V1_SENSE directly connected to power blades 6 to 10 (inclusive)

2. V1_SENSE_RTN directly connected to power blades 1 to 5 (inclusive)

Compensation for up to 0.12Vdc total

connection drop (output and return

connections).

ISHARE

Bi-

Directional

Analogue

Bus

The current sharing signal is connected between sharing units (forming an ISHARE bus). It is an

input and/or an output (bi-directional analogue bus) as the voltage on the line controls the

current share between sharing units. A power supply will respond to a change in this voltage

but a power supply can also change the voltage depending on the load drawn from it. On a

single unit the voltage on the pin (and the common ISHARE bus would read 8VDC at 100% load

(module capability). For two identical units sharing the same 100% load this would read 4VDC

for perfect current sharing (i.e. 50% module load capability per unit).

Analogue voltage:

+8V maximum; 10K to +12V_RTN