Microstepping DMOS Driver with Translator

A5979

9

Allegro MicroSystems, LLC

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

www.allegromicro.com

Step Input (STEP)

A low-to-high transition on the STEP input sequences the transla-

tor and advances the motor one increment. The translator controls

the input to the DACs and the direction of current flow in each

winding. The size of the increment is determined by the state of

inputs MS1 and MS2 (see Table 1).

Microstep Select (MS1 and MS2)

Input terminals MS1 and MS2 select the microstepping format

per Table 1. Changes to these inputs do not take effect until the

STEP command.

Direction Input (DIR)

The state of the DIR input will determine the direction of rotation

of the motor.

Percent Fast-Decay Input (PFD)

When a STEP input command results in a lower output current

than the previous step, it switches the output current decay for

that bridge to either slow-, fast-, or mixed-decay, depending on

the voltage level at the PFD input. If the voltage at the PFD input

is selected. Mixed-decay is selected when the voltage on the

PFD input is between these two levels. This terminal should be

decoupled with a 0.1 µF capacitor.

Mixed-Decay Operation

input command results in a lower output current that the previous

step. As the trip point is reached, the bridge will go into fast-

decay mode until the voltage on the RC terminal decays to the

voltage applied to the PFD terminal. The time the bridge remains

in fast-decay is approximated by:

decay mode for the remainder of the fixed off-time period.

Reset Input (RESETn)

The RESETn input (active low) sets the translator to a predefined

home state (see figures for home state conditions) and turns off

all of the DMOS outputs. The HOMEn output goes low and all

STEP inputs are ignored until the RESETn input goes high.

Home Output (HOMEn)

The HOMEn output is a logic output indicator of the initial state

of the translator. At power-up, the translator is reset to the home

state (see figures for home state conditions), and the HOMEn

output will be low. When the translator is not in the home state,

this output is high.

Synchronous Rectification

When a PWM off-cycle is triggered by an internal current con-

trol, load current will recirculate according to the decay mode

selected by the control logic. The A5979 synchronous rectifica-

tion feature will turn on the appropriate MOSFETs during the

current decay and effectively short out the body diodes with the

cantly and eliminate the need for external Schottky diodes for

most applications.

The synchronous rectification can be set in either active mode or

disabled mode using the SR pin.

Synchronous Rectification Mode (SR)

When the SR input is logic-low, active mode is enabled and syn-

chronous rectification will occur. Reversal of the current in the

motor winding is prevented when using this mode by turning off

synchronous rectification if the current in the winding decays to

zero. When the SR input is logic-high, synchronous rectification

is disabled. Synchronous rectification is typically disabled only

when external diodes are required to transfer power dissipation

from the A5979 package to the external diodes.

Enable Input (ENABLEn)

This active-low input enables all of the DMOS outputs. When

logic-high, the outputs are disabled. Inputs to the transla-

tor (STEP, DIR, MS1, MS2) are all active independent of the

ENABLEn input state.

Sleep Mode (SLEEPn)

This active-low input is used to minimize power consumption

when the device is not in use. Sleep mode disables much of the

internal circuitry, including the output DMOS, regulator, and

charge pump. A logic-high allows normal operation and a rising

edge on this input resets the translator to the home position.

When coming out of sleep mode, 1 ms is required before issuing

a STEP command, to allow the charge pump to stabilize.