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A6274 Datasheet(PDF) 6 Page - Allegro MicroSystems |
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A6274 Datasheet(HTML) 6 Page - Allegro MicroSystems |
6 / 24 page Linear Current Regulator and Controller for Automotive LED Arrays A6274, A6274-1 A6284, A6284-1 6 Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com Characteristics Symbol Test Conditions Min. Typ. Max. Unit PROTECTION VIN Required to Derate ILED by 10% VINth(L) VVTH = 1.84 V 19 20 21 V VIN Derating Range (VINth(L) to VINth(H)) VINthd ILED drops from 90% to 50% level – 6.4 – V MOSFET Drain Short Protection Threshold VOUT(SC) Measure across OUT and GND pins – 1 – V MOSFET Drain Short Protection Blank Delay td(OUT,scblnk) Protection disabled from enable instance – 1 – ms String Short Detect Voltage VSC(STRING) While LED sinks are in regulation; sensed from VLEDx to VLEDreg, 5 V < VIN < 18 V 1.8 – 2.6 V LEDx Not-In-Use Voltage VLEDx(NULL) Detect during tLEDdet time period 0.18 0.26 0.34 V LEDx Pin Source Current ILEDsrc Source current for Not-In-Use Detection 65 – 95 μA LED Connected Detect Time tLEDdet ENx = high and VGATE ≤ (VIN – 3.3) at startup – 5 – ms LEDx Short-to-Ground Detect Voltage VLED(SC) − − 0.16 V Open-LED Disable Voltage VOLED_dis Measured at OUT pin, VVTH = 2 V – 10 – V Input Overvoltage Threshold VVINOV VEN1 = VEN2 = high – 43 – V Thermal Monitor Activation Temperature2 TJM TJ where ILED drops to 90% level – TJF – 21 – °C Thermal Monitor Low-Current Temperature2 TJL TJ where ILED drops to 35% level – TJF – 7 – °C Overtemperature Shutdown2 TJF Temperature increasing − 175 − °C Overtemperature Hysteresis2 TJ(HYS) Recovery = TJF – TJ(HYS) − 30 − °C PWM DIMMING: INTERNAL AND EXTERNAL Internal-to-External PWM Mode Delay td(PWM,INEX) − 1 − µs External-to-Internal PWM Mode Delay td(PWM,EXIN) VPWMIN < VLOGIC(L) − 20 − ms PWM DIMMING INTERNAL Maximum PWM-Dimming Frequency fPWM(MAX) 7.15 kΩ between PWMIN and GND − 2050 − Hz Minimum PWM-Dimming Frequency fPWM(MIN) 71.5 kΩ between PWMIN and GND 195 215 235 Hz PWM Duty Cycle DPWM52 DR driven by resistor divider from BIAS, VBIAS ÷ VDR = 27.78, PWM = 205 Hz to 2 kHz ● 4.5 5.0 5.5 % DPWM90 DR driven by resistor divider from BIAS, VBIAS ÷ VDR = 1.54, PWM = 205 Hz to 2 kHz 87 90 93 % VDRDC(MAX) Minimum required voltage on DR for 100% duty cycle 3.6 − − V DR Pin Current1 IDR(SRC) VDR = 2 V − − 1 μA ELECTRICAL CHARACTERISTICS (continued): Valid at VIN = 14 V, VENx = 3.3 V; ● indicates specifications across the full operating tempera- ture range with TJ = –40°C to 150°C; other specifications are at TJ = 25°C, unless noted otherwise. Refer to Figure 1 for typical application circuit. Continued on the next page… |
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