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BD81026MUV-E2 Datasheet(PDF) 7 Page - Rohm

Part # BD81026MUV-E2
Description  Gamma voltage generated IC with built-in DAC
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Manufacturer  ROHM [Rohm]
Direct Link  http://www.rohm.com
Logo ROHM - Rohm

BD81026MUV-E2 Datasheet(HTML) 7 Page - Rohm

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TSZ02201-0313AAF00660-1-2
© 2016 ROHM Co., Ltd. All rights reserved.
19.Feb.2016 Rev.001
www.rohm.com
TSZ22111・15・001
BD81026MUV
Operation of each block
(1) 10 Bit DAC block
■Serial data control block
The serial interface uses a 2-line serial data format (SCL, SDA).
The serial data control block consists of a register that stores data from the SDA and SCL pins, and a DAC circuit that
receives the output from this register and provides adjusted voltages to other IC blocks.
Figure 3. Serial block
・Register ( Ch0 to Ch11 )
A serial signal (consisting of 10-bit gamma correction voltage values) input using the serial interface or I2C bus interface is
held for each register address.
Data is initialized by the reset signal generated during a power-on reset.
Register is selectable by BKSEL pin. (For detail, refer to P.9.)
Also, it is selectable that either revises the DAC output setting voltage by LD pin to the data, read to register.
(For detail, refer to P.10. )
・Data writing mode selector
Switching MODE pin High/Low enables changing data switching mode.
During MODE=Low, a data is rewrote by Double Register switching function of BKSEL control.
During MODE=High, a data is rewrote by DAC output latch function of LD control.
MODE pin is pulled down inside so that at open state, it is Low.
If it is set to High, connect to VDD.
・DAC
The DAC LOGIC converts the 10-bit digital signal read to the register to a voltage.
・AMP ( Ch0 to Ch11 )
The Amp amplifies the voltage output from the DAC LOGIC.
While Under Voltage Lock-Out (UVLO) circuit or Thermal Shut Down (TSD) circuit is operating, output goes into Hi-z.
In case connecting high capacity capacitor with low ESR, damping is needed with a resistor to keep phase margin.
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT10
OUT11
Acknowledge
SDA
SCL
Shift Register
DAC
DAC
DAC
DAC
DAC
DAC
DAC
DAC
DAC
DAC
DAC
DAC
BKSEL
LD
MUX
MUX
MUX
MUX
MUX
MUX
MUX
MUX
MUX
MUX
MUX
MUX
Register11 BANK B
Register11 BANK A
Register10 BANK B
Register10 BANK A
Register9 BANK B
Register9 BANK A
Register8 BANK B
Register8 BANK A
Register7 BANK B
Register7 BANK A
Register6 BANK B
Register6 BANK A
Register5 BANK B
Register5 BANK A
Register4 BANK B
Register4 BANK A
Register3 BANK B
Register3 BANK A
Register2 BANK B
Register2 BANK A
Register1 BANK B
Register1 BANK A
Register0 BANK B
Register0 BANK A
CTL
MODE


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