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BM81110MUW Datasheet(PDF) 6 Page - Rohm |
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BM81110MUW Datasheet(HTML) 6 Page - Rohm |
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6 / 50 page  6/46 TSZ02201-0313AAF00410-1-2 © 2014 ROHM Co., Ltd. All rights reserved. 2015.08.10 Rev.002 www.rohm.com TSZ22111 • 15 • 001 BM81110MUW Description of each Block ① BUCK CONVERTER BLOCK 1 This block generates VIO (VDD1) voltage from Power supply voltage. After releasing UVLO of VIN, VL starts activating. After Auto Read is operated to EEPROM, VIO will be activated. Power on Reset works at the time of VIN startup and the setting written to EEPROM will be reflected in Register. During operation, it is possible to prevent destruction of IC by OVP, UVP and OCP protection functions. ② BUCK CONVERTER BLOCK 2 This block generates VCORE (VDD2) voltage from Power supply voltage of VIO. After completing VIO start-up, VCORE starts activating. Power on Reset works at the time of VIN startup and the setting written to EEPROM will be reflected in Register. During operation, it is possible to prevent destruction of IC by OVP, UVP and OCP protection functions. ③ VGL REGULATOR BLOCK This block generates VGL voltage. After completing VCORE start-up, VGL starts activating. Power on Reset works at the time of VIN startup and the setting written to EEPROM will be reflected in Register. During operation, it is possible to prevent destruction of IC by UVP and OCP protection functions. ④ BOOST CONVERTER BLOCK This block generates AVDD (SWO) voltage from Power supply voltage. It activates when EN=H, and under condition where VIO and VGL are active. Power on Reset works at the time of VIN startup and the setting written to EEPROM will be reflected in Register. During operation, it is possible to prevent destruction of IC by OVP, UVP and OCP protection functions. ⑤ BUCK CONVERTER BLOCK 3 This block generates HAVDD (VDD3) voltage from Power supply voltage. HAVDD starts up following AVDD output voltage. The setting voltage range of the HAVDD voltage depends on the AVDD setting voltage, and the lower limit level of the HAVDD voltage is limited to AVDD×0.4. Power on Reset works at the time of VIN startup and the setting written to EEPROM will be reflected in Register. During operation, it is possible to prevent destruction of IC by OVP, UVP and OCP protection functions. ⑥ VGH REGULATOR BLOCK This block generates VGH voltage from AVDD voltage. After completing AVDD star-up, VGH starts activating. Power on Reset works at the time of VIN startup and the setting written to EEPROM will be reflected in Register. During operation, it is possible to prevent destruction of IC by OVP, UVP and OCP protection functions. ⑦ GPM BLOCK This is a switching circuit to drive a gate voltage for TFT consisted of PMOS FET. VGHM output synchronizes with CTRL input and outputs High voltage = VGH at CTRL=H. GPM Falling Limit voltage can be controlled by EEPROM. ※ Caution ・EN Input tolerant function is built-in. No need to be always EN < VIN. ・When FAULT pin is not used, FAULT pin must be connected to GND, or it should be open. ・When NTC pin is not used, NTC pin must be connected to GND. ・When HVS pin is not used, HVS pin must be connected to GND. |
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