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HV9113NG-G Datasheet(PDF) 10 Page - Microchip Technology |
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HV9113NG-G Datasheet(HTML) 10 Page - Microchip Technology |
10 / 18 page HV9110/HV9112/HV9113 DS20005505A-page 10 2016 Microchip Technology Inc. 5.0 DETAILED DESCRIPTION 5.1 High-Voltage Regulator The high-voltage regulator included in HV9110/HV9112/HV9113 consists of a high-voltage N- channel Depletion-mode DMOS transistor driven by an error amplifier, providing a current path between the VIN terminal and the VDD terminal. The maximum cur- rent, about 20 mA, occurs when VDD = 0, with current reducing as VDD rises. This path shuts off when VDD rises to somewhere between 8V and 9.4V. So, if VDD is held at 10V or 12V by an external source, no current other than leakage is drawn through the high voltage transistor. This minimizes dissipation within the high- voltage regulator. Use an external capacitor between VDD and GND. This capacitor should have good high-frequency character- istics. Ceramic caps work well. The device uses a compound resistor divider to monitor VDD for both the undervoltage lockout circuit and the shutoff circuit of the high-voltage FET. Setting the undervoltage sense point about 0.6V lower on the string than the FET shutoff point guarantees that the undervoltage lockout releases before the FET shuts off. 5.2 Bias Circuit HV9110/HV9112/HV9113 require an external bias resistor, connected between the Bias pin and GND, to set currents in a series of current mirrors used by the analog sections of the chip. The nominal external bias current requirement is 15 µA to 20 µA, which can be set by a 390 kΩ to 510 kΩ resistor if VDD = 10V, or a 510 kΩ to 680 kΩ resistor if VDD = 12V. A precision resistor is not required, ±5% meets device require- ments. 5.3 Clock Oscillator The clock oscillator of the HV9110/HV9112/HV9113 consists of a ring of CMOS inverters, timing capacitors, and a capacitor-discharge FET. A single external resis- tor between the OSCI and OSCO sets the oscillator fre- quency. (See Figure 2-4.) The HV9110 and HV9112 include a frequency-dividing flip-flop that allows the part to operate with a 50% duty limit. Accordingly, the effective switching frequency of the power converter is half the oscillator frequency. (See Figure 2-4.) An internal discharge FET resets the oscillator ramp at the end of the oscillator cycle. The discharge FET is externally connected to GND, by way of a resistor. The resistor programs the oscillator dead time at the end of the oscillator period. The oscillator turns off during shutdown to reduce sup- ply current by about 150 μA. 5.4 Reference The reference of the HV9110/HV9112/HV9113 consists of a band-gap reference, followed by a buffer amplifier, which scales the voltage up to 4V. The scaling resistors of the buffer amplifier are trimmed during manufacture so that the output of the error amplifier, when con- nected in a gain of –1 configuration, is as close to 4V as possible. This nulls out the input offset of the error amplifier. As a consequence, even though the observed reference voltage of a specific part may not be exactly 4V, the feedback voltage required for proper regulation will be 4V. An approximately 50 kΩ resistor is located internally between the output of the reference buffer amplifier and the circuitry it feeds—reference output pin and non-inverting input to the error amplifier. This allows overriding the internal reference with a low impedance voltage source ≤ 6V. Using an external reference rein- states the input offset voltage of the error amplifier. Overriding the reference should seldom be necessary. The reference of the HV9110/HV9112/HV9113 is a high-impedance node, and usually there will be signifi- cant electrical noise nearby. Therefore, a bypass capacitor between the reference pin and GND is strongly recommended. The reference buffer amplifier is compensated to be stable with a capacitive load of 0.01 µF to 0.1 µF. 5.5 Error Amplifier The error amplifier on HV9110/HV9112/HV9113 is a low-power, differential-input, operational amplifier. A PMOS input stage is used, so the common mode range includes ground and the input impedance is high. 5.6 Current Sense Comparators The HV9110/HV9112/HV9113 use a dual-comparator system with independent comparators for modulation and current limiting. This provides the designer greater latitude in compensation design, as there are no clamps, except ESD protection, on the compensation pin. 5.7 Remote Shutdown The NSD and RST pins control the shutdown latch. These pins have internal current-source pull-ups so they can be driven from open drain logic. When not used they should be left open or connected to VDD. |
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