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MC100LVEL90DWG Datasheet(PDF) 1 Page - ON Semiconductor |
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MC100LVEL90DWG Datasheet(HTML) 1 Page - ON Semiconductor |
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1 / 5 page  © Semiconductor Components Industries, LLC, 2016 July, 2016 − Rev. 12 1 Publication Order Number: MC100LVEL90/D MC100LVEL90 -3.3 V / -5 V Triple ECL Input to LVPECL Output Translator Description The MC100LVEL90 is a triple ECL to LVPECL translator. The device receives either −3.3 V or −5 V differential ECL signals, determined by the VEE supply level, and translates them to +3.3 V differential LVPECL output signals. To accomplish the level translation, the LVEL90 requires three power rails. The VCC supply should be connected to the positive supply, and the VEE pin should be connected to the negative power supply. The GND pins, as expected, are connected to the system ground plane. Both VEE and VCC should be bypassed to ground via 0.01 mF capacitors. Under open input conditions, the D input will be biased at VEE/2 and the D input will be pulled to VEE. This condition will force the Q output to a LOW, ensuring stability. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. Features • 500 ps Propagation Delays • ESD Protection: > 2 kV HBM, > 200 V MM • The 100 Series Contains Temperature Compensation • Operating Range: VCC = 3.0 V to 3.8 V; VEE = −3.0V to −5.5 V; GND = 0 V • Internal Input Pulldown Resistors • Q Output will Default LOW with Inputs Open or at VEE • Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test • Moisture Sensitivity: Level 3 (Pb-Free) For Additional Information, see Application Note AND8003/D • Flammability Rating: UL 94 V−0 @ 0.125 in, Oxygen Index: 28 to 34 • Transistor Count = 261 devices • These Devices are Pb-Free, Halogen Free and are RoHS Compliant www.onsemi.com *For additional marking information, refer to Application Note AND8002/D. MARKING DIAGRAM* A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G = Pb-Free Package SOIC−20 WB DW SUFFIX CASE 751D 20 1 100LVEL90 AWLYYWWG †For information on tape and reel specifications, in- cluding part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. ORDERING INFORMATION Device Package Shipping† MC100LVEL90DWG SOIC−20 WB (Pb-Free) 38 Units/Tube MC100LVEL90DWR2G SOIC−20 WB (Pb-Free) 1000/Tape & Reel |
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