© Semiconductor Components Industries, LLC, 2016

July, 2016 − Rev. 1

1

Publication Order Number:

MC100LVELT20/D

MC100LVELT20

3.3V LVTTL/LVCMOS to

Differential LVPECL

Translator

Description

The MC100LVELT20 is a 3.3 V TTL/CMOS to differential PECL

translator. Because PECL (Positive ECL) levels are used, only + 3.3 V

and ground are required. The small outline SOIC−8 package and the

single gate of the MC100LVELT20 makes it ideal for those

applications where space, performance, and low power are at a

premium.

The 100 Series contains temperature compensation.

Features

A

= Assembly Location

L

= Wafer Lot

Y

= Year

W

= Work Week

G

= Pb-Free Package

MARKING DIAGRAM

SOIC−8 NB

D SUFFIX

CASE 751−07

www.onsemi.com

KVT20

ALYW

G

1

8

1

8

*For additional marking information, refer to

Application Note AND8002/D.

†For information on tape and reel specifications, in-

cluding part orientation and tape sizes, please refer

to our Tape and Reel Packaging Specifications

Brochure, BRD8011/D.

ORDERING INFORMATION

Device

Package

MC100LVELT20DG

SOIC−8 NB

(Pb-Free)

98 Units/Tube

MC100LVELT20DR2G SOIC-8 NB

(Pb-Free)

2500/Tape & Reel