MC100LVEP34DG datasheet(2/11 Pages) ONSEMI

Part #	MC100LVEP34DG

Description	2.5V / 3.3V ECL Clock Generation Chip

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MC100LVEP34

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2

VCC

Q0

Q1

VCC

Q2

15

16

14

13

12

11

10

2

1

3

4

5

6

7

VCC

9

8

EN

NC

CLK

VBB

MR

VEE

D

Q

R

Q

R

÷2

Q

R

÷4

Q

R

÷8

Warning: All VCC and VEE pins must be externally connected

to Power Supply to guarantee proper operation.

Q0

Q1

Q2

Figure 1. 16−Lead Pinout (Top View) and Logic Diagram

Table 1. PIN DESCRIPTION

Function

CLK*, CLK**

ECL Diff Clock Inputs

EN*

ECL Sync Enable

MR*

ECL Master Reset

Q0, Q0

ECL Diff

÷2 Outputs

Q1, Q1

ECL Diff

÷4 Outputs

Q2, Q2

ECL Diff

÷8 Outputs

VBB

Reference Voltage Output

VCC

Positive Supply

VEE

Negative Supply

NC

No Connect

* Pins will default LOW when left open.

**Pins will default to VCC/2 when left open.

Table 2. FUNCTION TABLE

CLK

EN

MR

FUNCTION

Z

ZZ

X

L

H

X

L

H

Divide

Hold Q0−3

Reset Q0−3

Z = Low−to−High Transition

ZZ = High−to−Low Transition

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