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TM248CBK32S-60 Datasheet(PDF) 2 Page - Texas Instruments |
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TM248CBK32S-60 Datasheet(HTML) 2 Page - Texas Instruments |
2 / 11 page TM124BBK32, TM124BBK32S 1048576 BY 32-BIT TM248CBK32, TM248CBK32S 2097152 BY 32-BIT DYNAMIC RAM MODULE SMMS132D – JANUARY 1991 – REVISED JUNE 1995 2 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TM248CBK32 The TM248CBK32 operates as sixteen TMS44400DJs connected as shown in the functional block diagram. Refer to the TMS44400 data sheet for details of operation. The common I/O feature of the TM248CBK32 dictates the use of early write cycles to prevent contention on D and Q. refresh Refresh period is extended to 16 ms and, during this period, each of the 1024 rows must be strobed with RAS in order to retain data. A0-A9 address lines must be refreshed every 16 ms as required by the TMS44400 DRAM. CAS can remain high during the refresh sequence to conserve power. single in-line memory module and components PC substrate: 1,27 ± 0,1 mm (0.05 inch) nominal thickness; 0.005 inch/inch maximum warpage Bypass capacitors: Multilayer ceramic Contact area for TM124BBK32 AND TM248CBK32: Nickel plate and gold plate over copper. Contact area for TM124BBK32S AND TM248CBK32S: Nickel plate and tin-lead over copper. |
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