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TMS320C6414TBGLZA6 Datasheet(PDF) 2 Page - Texas Instruments |
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TMS320C6414TBGLZA6 Datasheet(HTML) 2 Page - Texas Instruments |
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2 / 142 page  TMS320C6414T, TMS320C6415T, TMS320C6416T FIXEDPOINT DIGITAL SIGNAL PROCESSORS SPRS226J − NOVEMBER 2003 − REVISED JULY 2006 2 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Table of Contents reset 75 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . absolute maximum ratings over operating case temperature range 76 . . . . . . . . . . . . . . . . . . . . . . . . . . recommended operating conditions 76 . . . . . . . . . . . . . . . . electrical characteristics over recommended ranges of supply voltage and operating case temperature 77 . recommended clock and control signal transition behavior 77 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . parameter measurement information 78 . . . . . . . . . . . . . . . input and output clocks 80 . . . . . . . . . . . . . . . . . . . . . . . . . . . asynchronous memory timing 85 . . . . . . . . . . . . . . . . . . . . . programmable synchronous interface timing 89 . . . . . . . . synchronous DRAM timing 94 . . . . . . . . . . . . . . . . . . . . . . . . HOLD/HOLDA timing 104 . . . . . . . . . . . . . . . . . . . . . . . . . . . BUSREQ timing 105 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . reset timing 106 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . external interrupt timing 108 . . . . . . . . . . . . . . . . . . . . . . . . . host-port interface (HPI) timing 109 . . . . . . . . . . . . . . . . . . . peripheral component interconnect (PCI) timing [C6415T and C6416T only] 114 . . . . . . . . . . . . . . . . . . multichannel buffered serial port (McBSP) timing 117 . . . . UTOPIA slave timing [C6415T and C6416T only] 128 . . . timer timing 131 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . general-purpose input/output (GPIO) port timing 132 . . . . JTAG test-port timing 133 . . . . . . . . . . . . . . . . . . . . . . . . . . . mechanical data 134 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . revision history 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GLZ, ZLZ and CLZ BGA packages (bottom view) 4 . . . . . . . . description 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . device characteristics 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . device compatibility 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . functional block and CPU (DSP core) diagram 8 . . . . . . . . . . . CPU (DSP core) description 9 . . . . . . . . . . . . . . . . . . . . . . . . . . memory map summary 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . peripheral register descriptions 15 . . . . . . . . . . . . . . . . . . . . . . . EDMA channel synchronization events 28 . . . . . . . . . . . . . . . . interrupt sources and interrupt selector 30 . . . . . . . . . . . . . . . . signal groups description 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . device configurations 37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . multiplexed pins 40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . debugging considerations 40 . . . . . . . . . . . . . . . . . . . . . . . . . . . terminal functions 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . development support 62 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . device support 63 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . clock PLL 66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . general-purpose input/output (GPIO) 69 . . . . . . . . . . . . . . . . . . power-down mode logic 70 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . power-supply sequencing 72 . . . . . . . . . . . . . . . . . . . . . . . . . . . . power-supply decoupling 73 . . . . . . . . . . . . . . . . . . . . . . . . . . . . IEEE 1149.1 JTAG compatibility statement 74 . . . . . . . . . . . . . EMIF device speed 74 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . bootmode 75 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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