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TMS320C6414TGLZ1 Datasheet(PDF) 68 Page - Texas Instruments |
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TMS320C6414TGLZ1 Datasheet(HTML) 68 Page - Texas Instruments |
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68 / 142 page  TMS320C6414T, TMS320C6415T, TMS320C6416T FIXEDPOINT DIGITAL SIGNAL PROCESSORS SPRS226J − NOVEMBER 2003 − REVISED JULY 2006 68 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 clock PLL (continued) Table 31. TMS320C64x PLL Multiply Factor Options, Clock Frequency Ranges, and Typical Lock Time†‡ GLZ, ZLZ and CLZ PACKAGES − 23 x 23 mm BGA CLKMODE1 CLKMODE0 CLKMODE (PLL MULTIPLY FACTORS) CLKIN RANGE (MHz) CPU CLOCK FREQUENCY RANGE (MHz) CLKOUT4 RANGE (MHz) CLKOUT6 RANGE (MHz) TYPICAL LOCK TIME ( µs)§ 0 0 Bypass (x1) 0−100 0−100 0−25 0−16.6 N/A 0 1 x6 42−75 252−450 63−112.5 42−75 1 0 x12 42−75 504−900 126−225 84−150 75 1 1 x20 25−50 500−1000 125−250 83.3−166.6 75 † These clock frequency range values are applicable to a C64x−600, −720, −850, and −1000-MHz speed devices. For more detailed information, see the CLKIN timing requirements table for the specific device speed. ‡ Use external pullup resistors on the CLKMODE pins (CLKMODE1 and CLKMODE0) to set the C64x device to one of the valid PLL multiply clock modes (x6, x12, or x20). With internal pulldown resistors on the CLKMODE pins (CLKMODE1, CLKMODE0), the default clock mode is x1 (bypass). § Under some operating conditions, the maximum PLL lock time may vary by as much as 150% from the specified typical value. For example, if the typical lock time is specified as 100 µs, the maximum value may be as long as 250 µs. |
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