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TMS28F512A-17C4FML Datasheet(PDF) 10 Page - Texas Instruments |
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TMS28F512A-17C4FML Datasheet(HTML) 10 Page - Texas Instruments |
10 / 21 page Write Erase-Verify Command Setup Last Address? Start Increment Address Read and Verify Byte Write Set-Up-Erase Command X = X + 1 Wait = 10 ms Pass Write Read Command X = 1000? All Bytes = 00h? Interactive Mode Write Erase Command Program All Bytes to 00h Apply VPPL Power Down Apply VPPL Address = 00h VCC = 5 V ± 10%, VPP = 12 V ± 5% X = 1 Device Passed Device Failed No Yes No Yes Fail No Yes Wait = 6 µs Preprogram TMS28F512A 65536 BY 8-BIT FLASH MEMORY SMJS514C – FEBRUARY 1994 – REVISED AUGUST 1997 10 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 Bus Operation Command Comments Entire memory must = 00h before erasure Use Fastwrite programming algorithm Initialize addresses Standby Wait for VPP to ramp to VPPH (see Note A) Initialize pulse count Write Set-Up-Er ase Data = 20h Write Erase Data = 20h Standby Wait = 10 ms Write Erase-Veri fy Addr = Byte to verify; Data = A0h; ends the erase operation Standby Wait = 6 µs Read Read byte to verify erasure; compare output to FFh Write Read Data = 00h; resets register for read operations Standby Wait for VPP to ramp to VPPL (see Note B) NOTES: A. Refer to the recommended operating conditions for the value of VPPH. B. Refer to the recommended operating conditions for the value of VPPL. Figure 2. Flash-Erase Flowchart: Fasterase Algorithm |
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