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TMS320C6414TGLZ8 Datasheet(PDF) 97 Page - Texas Instruments |
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TMS320C6414TGLZ8 Datasheet(HTML) 97 Page - Texas Instruments |
97 / 142 page TMS320C6414T, TMS320C6415T, TMS320C6416T FIXEDPOINT DIGITAL SIGNAL PROCESSORS SPRS226J − NOVEMBER 2003 − REVISED JULY 2006 97 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 SYNCHRONOUS DRAM TIMING (CONTINUED) ECLKOUTx CEx ABE[7:0] or BBE[1:0] AEA[12:3] or BEA[10:1] AED[63:0] or BED[15:0] AOE/SDRAS/SOE‡ ARE/SDCAS/SADS/SRE‡ AWE/SDWE/SWE‡ AEA13 or BEA11 AEA[22:14] or BEA[20:12] BE1 BE2 BE3 BE4 Bank Column D1 D2 D3 D4 11 8 9 5 5 5 4 2 11 8 9 4 4 2 1 10 3 4 WRITE PDT§ 14 14 † These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a “B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the synchronous DRAM memory access signals are shown as generic ( SDCAS, SDWE, and SDRAS ) instead of ASDCAS, ASDWE, and ASDRAS (for EMIFA) and BSDCAS, BSDWE, and BSDRAS (for EMIFB)]. ‡ ARE/SDCAS/SADS/SRE, AWE/SDWE/SWE, and AOE/SDRAS/SOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM accesses. § PDT signal is only asserted when the EDMA is in PDT mode (set the PDTD bit to 1 in the EDMA options parameter RAM). For PDT write, data is not driven (in High-Z). The PDTWL field in the PDT control register (PDTCTL) configures the latency of the PDT signal with respect to the data phase of a write transaction. The latency of the PDT signal for a write transaction can be programmed to 0, 1, 2, or 3 by setting PDTWL to 00, 01, 10, or 11, respectively. PDTWL equals 00 (zero latency) in Figure 28. Figure 28. SDRAM Write Command for EMIFA and EMIFB† |
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