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TMS418169P-60 Datasheet(PDF) 11 Page - Texas Instruments |
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TMS418169P-60 Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 67 page  TMS55160, TMS55161, TMS55170, TMS55171 262144 BY 16-BIT MULTIPORT VIDEO RAMS SMVS464 – MARCH1996 11 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 functional operation description random-access operation Table 4. DRAM Function Table RAS FALL CASx FALL ADDRESS DQ0 – DQ15† MNEMONIC FUNCTION CASx‡ TRG WE DSF DSF RAS CASx§ RAS CASL CASU WE MNEMONIC CODE Reserved (do not use) L L L L X X X X X — CBR refresh (no reset) and stop-point set¶ L X L H X Stop Point # X X X CBRS CBR refresh (option reset)|| L X H L X X X X X CBR CBR refresh (no reset)k L X H H X X X X X CBRN DRAM write (nonmasked) H H H L L Row Addr Col Addr X Valid Data RW DRAM write (nonpersistent write-per-bit) H H L L L Row Addr Col Addr Write Mask Valid Data RWM DRAM write (persistent write-per-bit) H H L L L Row Addr Col Addr X Valid Data RWM DRAM block write (nonmasked)h H H H L H Row Addr Block Addr X Col Mask BW DRAM block write (nonpersistent write-per-bit)h H H L L H Row Addr Block Addr Write Mask Col Mask BWM DRAM block write (persistent write-per-bit)h H H L L H Row Addr Block Addr X Col Mask BWM Load write-mask register ◊ H H H H L Refresh Addr X X Write Mask LMR Load color register H H H H H Refresh Addr X X Color Data LCR Legend: X = Don’t care Col Mask = H: Write to address/column enabled Write Mask = H: Write to I/O enabled † DQ0 – DQ15 are latched on either the falling edge of WE or the first falling edge of CASx, whichever occurs later. ‡ Logic L is selected when either or both CASL and CASU are low. § The column address, the block address, or the tap point is latched on the first falling edge of CASx depending upon which function is executed. ¶ CBRS cycle should be performed immediately after the power-up initialization for stop-point mode. # A0 – A3, A8: don’t care; A4 – A7 : stop-point code || CBR refresh (option reset) mode ends persistent write-per-bit mode and stop-point mode. kCBR refresh (no reset) mode does not end persistent write-per-bit mode or stop-point mode. hFor 4-column block write (TMS5516x), block address is A2–A8; for 8-column block write (TMS5517x), block address is A3–A8. ◊ Load-write-mask-register cycle sets the persistent write-per-bit mode. The persistent write-per-bit mode is reset only by the CBR (option reset) cycle. |
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