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TMS626812 Datasheet(PDF) 11 Page - Texas Instruments |
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TMS626812 Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 40 page  TMS626812 1048576 BY 8-BIT BY 2-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY SMOS687A –JULY 1996 – REVISED APRIL 1997 11 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 interrupted bursts (continued) Table 7. Read-Burst Interruption INTERRUPTING COMMAND EFFECT OR NOTE ON USE DURING READ BURST READ, READ-P Current output cycles continue until the programmed latency from the superseding READ (READ-P) command is met and new output cycles begin (see Figure 2). WRT, WRT-P The WRT (WRT-P) command immediately supersedes the read burst in progress. To avoid data contention, DQM must be high before the WRT (WRT-P) command to mask output of the read burst on cycles (nCCD–1), nCCD, and (nCCD+1) assuming that there is any output on these cycles. (see Figure 3). DEAC, DCAB The DQ bus is in the high-impedance state when nHZP cycles are satisfied or when the read burst completes, whichever occurs first (see Figure 4). CLK DQ READ Command at Column Address C0 C0 C0 + 1 C1 C1 + 1 Interrupting READ Command at Column Address C1 b) INTERRUPTED ON EVEN CYCLES CLK DQ READ Command at Column Address C0 C0 C1 C1 + 1 C1 + 2 Interrupting READ Command at Column Address C1 a) INTERRUPTED ON ODD CYCLES nCCD = Two cycles nCCD = One Cycle Output Burst for the Interrupting READ Command Begins Here Output Burst for the Interrupting READ Command Begins Here NOTE A: For these examples assume CAS latency = 3, and burst length = 4. Figure 2. Read Burst Interrupted by Read Command |
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