K6T4016U3C-RB10 datasheet(8/9 Pages) SAMSUNG

Part #	K6T4016U3C-RB10

Description	256Kx16 bit Low Power and Low Voltage CMOS Static RAM

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Manufacturer	SAMSUNG [Samsung semiconductor]

Direct Link	http://www.samsung.com/Products/Semiconductor

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8 / 9 page

K6T4016V3C, K6T4016U3C Family

CMOS SRAM

Revision 2.01

October 2001

8

Address

CS

Data Valid

UB, LB

WE

Data in

Data out

High-Z

TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB Controlled)

NOTES (WRITE CYCLE)

1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB

or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transi-

tion when CS goes high and WE goes high. The tWP is measured from the beginning of write to the end of write.

2. tCW is measured from the CS going low to the end of write.

3. tAS is measured from the address valid to the beginning of write.

4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS or WE going high.

tWC

tCW(2)

tBW

tWP(1)

tDH

tDW

tWR(4)

tAW

DATA RETENTION WAVE FORM

CS controlled

VCC

3.0/2.7V1)

2.2V

VDR

CS

GND

Data Retention Mode

CS

≥VCC - 0.2V

tSDR

tRDR

tAS(3)

1. 3.0V for K6T4016V3C Family, 2.7V for K6T4016U3C Family

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K6T4016U3C-RB10 Datasheet(PDF) 8 Page - Samsung semiconductor

K6T4016U3C-RB10 Datasheet(HTML) 8 Page - Samsung semiconductor

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