TMS28F010A

1048576-BIT FLASH

ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORY

SMJS012 – DECEMBER 1992 – REVISED NOVEMBER 1993

6

POST OFFICE BOX 655303

POST OFFICE BOX 1443

Table 1. Operation Modes

FUNCTION

MODE

VPP†

(1)

E

(22)

G

(24)

A0

(12)

A9

(26)

W

(31)

DQ0 – DQ7

(13 – 15, 17 – 21)

Read

VPPL

VIL

VIL

X

X

VIH

Data Out

Output Disable

VPPL

VIL

VIH

X

X

VIH

HI-Z

Read

Standby and Write Inhibit

VPPL

VIH

X

X

X

X

HI-Z

Algorithm Selection Mode

VPPL

VIL

VIL

VIL

VID

VIH

Mfr Equivalent Code 89h

Algorithm-Selection Mode

VPPL

VIL

VIL

VIH

VID

VIH

Device Equivalent Code B4h

Read

VPPH

VIL

VIL

X

X

VIH

Data Out

Read/

Output Disable

VPPH

VIL

VIH

X

X

VIH

HI-Z

Write

Standby and Write Inhibit

VPPH

VIH

X

X

X

X

HI-Z

Write

VPPH

VIL

VIH

X

X

VIL

Data In

NOTE: X can be VIL or VIH.

† VPPL ≤ VCC + 2 V; VPPH is the programming voltage specified for the device. For more details, refer to the recommended operating conditions.

operation

read/output disable

When the outputs of two or more TMS28F010As are connected in parallel on the same bus, the output of any

particular device in the circuit can be read with no interference from the competing outputs of other devices. To

read the output of the TMS28F010A, a low-level signal is applied to the E and G pins. All other devices in the

circuit should have their outputs disabled by applying a high-level signal to one of these pins.

standby and write inhibit

high CMOS level on E. In this mode, all outputs are in the high-impedance state. The TMS28F010A draws active

current when it is deselected during programming, erasure, or program/erase verification. It continues to draw

active current until the operation is terminated.

algorithm-selection mode

The algorithm-selection mode provides access to a binary code identifying the correct programming and erase

A0. All other addresses must be held low. A0 low selects the manufacturer equivalent code 89h, and A0 high

selects the device equivalent code B4h, as shown in the algorithm-selection mode table below:

IDENTIFIER

PINS

IDENTIFIER

A0

DQ7

DQ6

DQ5

DQ4

DQ3

DQ2

DQ1

DQ0

HEX

Manufacturer Equivalent Code

VIL

1

0

0

0

1

0

0

1

89

Device Equivalent Code

VIH

1

0

1

1

0

1

0

0

B4

NOTE: E = G = VIL, A1 – A8 = VIL, A9 = VID, A10 – A16 = VIL, VPP = VPPL.

programming and erasure

In the erased state, all bits are at a logic 1. Before erasing the device, all memory bits must be programmed to

a logic 0. Afterwards, the entire chip is erased. At this point, the bits, now logic 1s, can be programmed

accordingly. Refer to the Fastwrite and Fasterase algorithms for further detail.