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ADT7411ARQ-REEL Datasheet(PDF) 4 Page - Analog Devices |
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ADT7411ARQ-REEL Datasheet(HTML) 4 Page - Analog Devices |
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4 / 36 page  ADT7411 Rev. A | Page 4 of 36 Parameter1 Min Typ Max Unit Conditions/Comments ROUND ROBIN UPDATE RATE2 Time to complete one measurement cycle through all channels. Slow ADC @ 25°C Averaging On 125.4 ms AIN1 and AIN2 are selected on Pins 7 and 8. Averaging Off 17.1 ms AIN1 and AIN2 are selected on Pins 7 and 8. Averaging On 140.36 ms D+ and D– are selected on Pins 7 and 8. Averaging Off 12.11 ms D+ and D− are selected on Pins 7 and 8. Fast ADC @ 25°C Averaging On 9.26 ms AIN1 and AIN2 are selected on Pins 7 and 8. Averaging Off 578.96 µs AIN1 and AIN2 are selected on pins 7 and 8. Averaging On 24.62 ms D+ and D− are selected on Pins 7 and 8. Averaging Off 3.25 ms D+ and D− are selected on Pins 7 and 8. ON-CHIP REFERENCE3 Reference Voltage 2.25 V Temperature Coefficient 80 ppm/°C DIGITAL INPUTS1, 3 Input Current ±1 µA VIN = 0 V to VDD. VIL, Input Low Voltage 0.8 V VIH, Input High Voltage 1.89 V Pin Capacitance 3 10 pF All Digital Inputs. SCL, SDA Glitch Rejection 50 ns Input filtering suppresses noise spikes of less than 50 ns. DIGITAL OUTPUT Output High Voltage, VOH 2.4 V ISOURCE = ISINK = 200 µA. Output Low Voltage, VOL 0.4 V IOL = 3 mA. Output High Current, IOH 1 mA VOH = 5 V. Output Capacitance, COUT 50 pF INT/INT Output Saturation Voltage 0.8 V IOUT = 4 mA. I2C TIMING CHARACTERISTICS4, 5 Serial Clock Period, t1 2.5 µs Fast-Mode I2C. See Figure 2. Data In Setup Time to SCL High, t2 50 ns Data Out Stable after SCL Low, t3 0 ns See Figure 2. SDA Low Setup Time to SCL Low (Start Condition), t4 50 ns See Figure 2. SDA High Hold Time after SCL High (Stop Condition), t5 50 ns See Figure 2. SDA and SCL Fall Time, t6 90 ns See Figure 2. SPI TIMING CHARACTERISTICS1, 3, 6 CS to SCLK Setup Time, t1 0 ns See Figure 3. SCLK High Pulse Width, t2 50 ns See Figure 3. SCLK Low Pulse Width, t3 50 ns See Figure 3. Data Access Time after SCLK Falling Edge, t4 6 35 ns See Figure 3. Data Setup Time Prior to SCLK Rising Edge, t5 20 ns See Figure 3. Data Hold Time after SCLK Rising Edge, t6 0 ns See Figure 3. 2 Round robin is the continuous sequential measurement of the following channels: VDD, internal temperature, external temperature (AIN1, AIN2), AIN3, AIN4, AIN5, AIN6, AIN7, and AIN8. 3 Guaranteed by design and characterization, not production tested. 4 The SDA and SCL timing is measured with the input filters turned on so as to meet the FAST-Mode I2C specification. Switching off the input filters improves the transfer rate, but has a negative effect on the EMC behavior of the part. 5 Guaranteed by design. Not tested in production. 6 All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD), and timed from a voltage level of 1.6 V. |
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